Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.