Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: An electronic fuse comprising an integrated circuit having a control output terminal coupled to a control electrode of a power semiconductor switching device, the power semiconductor switching device being coupled in series with a load between first and second potentials, the integrated circuit further comprising a current sense input for sensing the current through the power semiconductor switching device, the integrated circuit further comprising a driver circuit for driving the power semi-conductor switching device, the driver circuit being coupled to a current limiting circuit responsive to the sensed current in the power semiconductor switching device, the current limiting circuit controlling the driver circuit whereby if the current through the power semiconductor switching device exceeds a predetermined threshold, the current limiting circuit generates a command to pulse the power semiconductor switching device on and off in a period of pulsed operation to maintain the current in the power semiconducto

Abstract: Apparatus for indirectly sensing the temperature of a power MOS device comprising a power MOS device having a current sense circuit for sensing the current in the power MOS device, a circuit for producing a voltage related to the drain-source voltage of the power MOS device, a comparator coupled to receive at a first input the voltage related to the drain-source voltage of the power MOS device and at a second input a voltage related to the current in the power MOS device, the comparator generating an overtemperature protection signal when a predetermined inequality between the voltages at the first and second inputs to the comparator occurs.

Abstract: A bootstrap capacitor charging circuit comprising first and second power switching transistors arranged in a half bridge arrangement such that the first and second transistors are disposed between a high side potential and a low side potential, a driver circuit for driving the first and second transistors, a bootstrap capacitor adapted to be charged from a potential source and for providing a voltage source to power an electronic circuit, a charging circuit providing a charging path from one of the high and low side potentials to the bootstrap capacitor, first and second series connected switches arranged between a common node of the first and second transistors and one of the high and low side potential, the bootstrap capacitor having a first terminal coupled to be charged by the charging circuit and a second terminal coupled to a common node between the first and second series connected switches; and a control circuit operating in first and second modes, wherein in a first mode when the first and second pow

Abstract: A MOS-gated circuit, including a plurality of gated switches; and a driver circuit electrically coupled to the gated switches, the driver circuit configured to automatically prevent a simultaneous conduction of the gated switches if at least one of the gated switches is not capable of sustaining a reapplied voltage without conducting.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A power switching circuit comprising a power semiconductor switching device, a charge pump circuit having a control input to control whether it is on or off and a charge pump output, the charge pump output being coupled to a control terminal of the power semiconductor switching device, a bootstrap power supply for supplying power to driver circuitry for the power semiconductor switching device, the bootstrap power supply comprising a bootstrap capacitor coupled to a charging current source, the bootstrap power supply providing power to the driver circuitry when the power semiconductor switching device is being switched by the driver circuitry in a pulsed mode, and the charge pump supplying a control voltage to turn on the power semiconductor switching device and maintain it on when the power switching semiconductor device is to be maintained on continuously.

Abstract: Apparatus for indirectly sensing the temperature of a power MOS device comprising a power MOS device having a current sense circuit for sensing the current in the power MOS device, a circuit for producing a voltage related to the drain-source voltage of the power MOS device, a comparator coupled to receive at a first input the voltage related to the drain-source voltage of the power MOS device and at a second input a voltage related to the current in the power MOS device, the comparator generating an overtemperature protection signal when a predetermined inequality between the voltages at the first and second inputs to the comparator occurs.

Abstract: Two switching half-bridges are operated to achieve constant power delivered to a resonant load while achieving a high power factor. A half-bridge connected to a circuit input draws a sinusoidal current that is in phase with the input voltage to achieve the high power factor. The two half-bridges are composed of two switches each, which are operated to obtain constant load power in satisfaction of calculated conduction angles. Alternatively, the switches are operated on complementary 50% duty cycles to regulate output voltage and shape the input current waveform. Output regulation is achieved by frequency control while input current wave shaping is realized by phase shifts between the two half-bridges.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A MOS-gated circuit, including a plurality of gated switches; and a driver circuit electrically coupled to the gated switches, the driver circuit configured to automatically prevent a simultaneous conduction of the gated switches if at least one of the gated switches is not capable of sustaining a reapplied voltage without conducting.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A solid state fuse type protective circuit is provided in which a series MOSFET is connected in series with the load and its voltage source and a shunt MOSFET is connected in parallel with the load. A control circuit turns the series MOSFET on and the shunt FET off under normal operation; and turns the series FET off and applies a turn on signal to the shunt FET under a fault condition. An indicator LED is connected across the series FET and turns on when the series FET turns off.

Abstract: Two switching half-bridges are operated to achieve constant power delivered to a resonant load while achieving a high power factor. A half-bridge connected to a circuit input draws a sinusoidal current that is in phase with the input voltage to achieve the high power factor. The two half-bridges are composed of two switches each, which are operated to obtain constant load power in satisfaction of calculated conduction angles. Alternatively, the switches are operated on complementary 50% duty cycles to regulate output voltage and shape the input current waveform. Output regulation is achieved by frequency control while input current wave shaping is realized by phase shifts between the two half-bridges.

Abstract: A lamp ballast drive circuit uses a resistor in place of a boot strap diode and drives a gas discharge illumination device. A pair of power devices are arranged in a half bridge configuration. A self oscillating driver circuit has output terminals connected to the power devices, respectively, a high side supply terminal, and a high side offset terminal that is coupled to the node between the power devices. A boot strap capacitor is coupled between the high side supply terminal and the high side offset terminal. A resistor is coupled between the voltage source and the high side supply terminal.

Abstract: A monolithic IGBT and control circuit therefor are integrated into a common chip. The IGBT is formed in a first area of the chip and the control circuit is formed in a second laterally spaced area and in a P well. Means are provided to prevent hole injection from the P.sup.+ substrate into the P well during IGBT operation. The means includes a sufficient spacing between the areas; a P.sup.+ collection region between the areas or an N.sup.+ diffusion between the areas which is connected to the P.sup.+ substrate. The areas are surrounded by a common field termination structure which, however, leaves a small surface bridge between the two areas. Control conductors from the control area to the IGBT area cross over the narrow area, and not over the field terminations. A lateral PNP transistor which is integrated in the chip and is external of the IGBT area is connected to the central N.sup.

Abstract: In a power integrated device having temperature monitoring circuits powered from input signal pulses, an overtemperature signal is memorized in a small capacitor (30 picofarads) to guarantee that the overtemperature signal will not be lost between two input pulses at a frequency greater than about 16 kHz. A larger charge storage capacitor (100 picofarads) is also added to store the input voltage V.sub.cc needed to power the overtemperature circuits.