Patents by Inventor Bruno Ghyselen

Bruno Ghyselen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7919393
    Abstract: A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 5, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
  • Patent number: 7902038
    Abstract: The invention relates to a method for production of a detachable substrate, comprising a method step for the production of an interface by means of fixing, using molecular adhesion, one face of a layer on one face of a substrate, in which, before fixing, a treatment stage for at least one of said faces is provided, rendering the mechanical hold at the interface at such a controlled level to be compatible with a subsequent detachment.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: March 8, 2011
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Bernard Aspar, Hubert Moriceau, Olivier Rayssac, Bruno Ghyselen
  • Publication number: 20110039368
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 17, 2011
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 7888235
    Abstract: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on a support substrate.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 15, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Publication number: 20100314628
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Patent number: 7803694
    Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 28, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Daniel Bensahel, Thomas Skotnicki
  • Publication number: 20100210090
    Abstract: A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
    Type: Application
    Filed: April 28, 2010
    Publication date: August 19, 2010
    Inventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
  • Publication number: 20100167500
    Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.
    Type: Application
    Filed: March 5, 2010
    Publication date: July 1, 2010
    Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Yves-Matthieu Le Vaillant
  • Patent number: 7741678
    Abstract: A semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layer of the intermediate layer. The support is made of a deposited material that has a lower quality than that of one or both of the intermediate and useful layers. A bonding layer may be included on one of the intermediate layer or the useful layer, or both, to facilitate bonding of the layers an a thin layer may be provided between the useful layer and intermediate layer. These final substrates are useful in optic, electronic, or optoelectronic applications.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: June 22, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7736988
    Abstract: A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: June 15, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
  • Patent number: 7655537
    Abstract: A method of fabricating composite substrates by associating a transfer layer with an intermediate support to form an intermediate substrate of predetermined thickness with the transfer layer having a free surface; providing a sample carrier having a surface and a recess that has a depth that is approximate the same as the predetermined thickness of the intermediate substrate so that the transfer layer free surface is positioned flush with the sample carrier surface; providing a support layer both on the transfer layer free surface and on a portion of the sample carrier surface surrounding the recess; removing the portion of the support layer that extends beyond the intermediate substrate; and detaching the transfer layer and support layer from its intermediate support to form the composite substrate. The support layer is made of a deposited material that has a lower quality than that of the intermediate support.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: February 2, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7648888
    Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: January 19, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Patent number: 7646038
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 12, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Publication number: 20090325362
    Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.
    Type: Application
    Filed: July 15, 2009
    Publication date: December 31, 2009
    Inventors: Nabil Chhaimi, Eric Guiot, Patrick Reynaud, Bruno Ghyselen, Cécile Aulnette, Bénédicte Osternaud, Takeshi Akatsu, Bruce Faure
  • Publication number: 20090289332
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Application
    Filed: August 5, 2009
    Publication date: November 26, 2009
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Patent number: 7622330
    Abstract: A method of fabricating composite substrates by associating a plurality of transfer layers in spaced relation upon a single intermediate support; providing a support layer on each transfer layer to form a composite substrate; and detaching the composite substrates from the intermediate support. The support layer is made of a deposited material that has a lower quality than that of the intermediate support. A bonding layer may be included on one of the intermediate support or the useful layer, or both, to facilitate bonding of the layers. The final substrates are useful in optic, electronic, or optoelectronic applications.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: November 24, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre
  • Patent number: 7615468
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: November 10, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Patent number: 7615463
    Abstract: The invention concerns a method for making thin layers containing microcomponents using a substrate. The method includes the following steps: a) provides a substrate; b) local implantation of at least a gaseous species in said substrate perpendicular to a plurality of implantation zones defined on the surface of the substrate, avoiding, by adequate selection of the depth and the shape of said implantation zones, degradation of said surface of the substrate during the step c); c) producing microcomponents in the surface layer of the substrate delimited by the implanting depth; and d) separating the substrate in two parts, one part containing the surface layer including said microcomponents, and the other the rest of the substrate. The invention is useful for producing microcomponents to be integrate on supports different from the those used for their manufacture.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: November 10, 2009
    Assignees: Commissariat a l'Energie Atomique, S.O.I. Tec Silicon On Insulator Technologies
    Inventors: Bernard Aspar, Christelle Lagahe, Bruno Ghyselen
  • Patent number: 7602046
    Abstract: The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: October 13, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Bruce Faure