Patents by Inventor Bryan Casper
Bryan Casper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11722128Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: June 24, 2021Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 11483186Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.Type: GrantFiled: September 19, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Bryan Casper, James Jaussi, Chintan Thakkar, Stefan Shopov
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Publication number: 20210320652Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 11070200Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: September 27, 2018Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20210168000Abstract: A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.Type: ApplicationFiled: September 19, 2018Publication date: June 3, 2021Inventors: Bryan Casper, James Jaussi, Chintan Thakkar, Stefan Shopov
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Publication number: 20200106430Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 8984189Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: GrantFiled: May 1, 2012Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8612809Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: GrantFiled: December 31, 2009Date of Patent: December 17, 2013Assignee: Intel CorporationInventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8571513Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: July 2, 2012Date of Patent: October 29, 2013Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20120281323Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: ApplicationFiled: July 2, 2012Publication date: November 8, 2012Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20120284436Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: ApplicationFiled: May 1, 2012Publication date: November 8, 2012Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 8213894Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: GrantFiled: December 29, 2005Date of Patent: July 3, 2012Assignee: Intel CorporationInventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
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Publication number: 20110161748Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Bryan Casper, Randy Mooney, Dave Dunning, Mozhgan Mansuri, James E. Jaussi
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Patent number: 7919984Abstract: A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.Type: GrantFiled: December 31, 2008Date of Patent: April 5, 2011Assignee: Intel CorporationInventors: Ganesh Balamurugan, Bryan Casper
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Publication number: 20100164539Abstract: A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Ganesh Balamurugan, Bryan Casper
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Publication number: 20070233444Abstract: In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Inventors: Frank O'Mahony, Haydar Kutuk, Bryan Casper, Eyal Fayneh, Sivakumar Mudanai, Wei-kai Shih, Farag Fattouh
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Publication number: 20070152746Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventors: Bryan Casper, Timothy Hollis, James Jaussi, Stephen Mooney, Frank O'Mahony, Mozhgan Mansuri
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Publication number: 20070153445Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen Mooney
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Publication number: 20070146011Abstract: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Moonkyun Maeng
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Publication number: 20070147491Abstract: According to embodiments of the subject matter disclosed in this application, transmit equalization, systematic jitter correction, and jitter injection may be achieved through a lookup table transmitter equalizer. The equalizer may be a multiple-way interleaving equalizer, with each interleaved section having its own lookup table. Entries in each lookup table may be modified to correct systematic jitters occurring in the received signal. Additionally, random errors may be injected to each lookup table. Injected errors are converted to both amplitude and phase modulation across a channel. By measuring the signal at the receiver, the characteristics of the transmission line may be obtained.Type: ApplicationFiled: December 22, 2005Publication date: June 28, 2007Inventors: Bryan Casper, James Jaussi