Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.

Abstract: A digital to analog converter (DAC) circuit operates least significant bit (LSB) first.

Abstract: A cyclic analog to digital converter (ADC) circuit operates to convert an analog input voltage into a digital output word. The ADC circuit includes an amplifier and capacitors configured as an integrator.

Abstract: In one embodiment, a decision feedback equalizer helps mitigate intersymbol interference in a bi-directional signaling environment. In the particular embodiment, the decision feedback equalizer includes a voltage-to-current converter to source a received differential current to first and second node, a latch to provide logic signal when comparing currents sourced to the first and second nodes, a memory unit to store the logic signals, and a mapping circuit to source first and second feedback currents to the first and second nodes. This embodiment further includes a transmitter to transmit data over a transmission line during receiving, and a digital-to-analog converter to provide a differential current to the first and second nodes to substantially cancel that part of the received differential currents contributed by the transmitter.

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering.

Abstract: In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering.

Abstract: In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering.

Abstract: A comparator unit comprising a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential amplifier having a pair of input nodes for receiving a differential signal and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes. The second amplifier stage is coupled to the pair of output nodes of the first amplifier stage. In one embodiment the second amplifier stage is a non-linear amplifier. In an alternative embodiment, the differential amplifier is a differential pair. In another alternative embodiment, the differential amplifier is a pair of differential pairs.

Abstract: An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.

Abstract: A receiver is calibrated using a transmitter that can output a plurality of substantially constant amplitude signals.

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+?[sgn{d(t)}?sgn{z(t)?Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, ? determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+?[sgn{d(t)}?sgn{z(t)?Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, ? determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

Abstract: A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset.