Abstract: The systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. The network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. The network chip is configured to allow the BMC to access a plurality of registers of the network chip via a Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: A method for efficiently processing and storing large data sets associated with a multi-stage bioinformatics analysis of genomic data is disclosed. The present method increases the efficiency of the electronic storage of these large data sets by automatically deleting or compressing intermediate data or a portion of output data and compressing input data, where both deletion and compression are based on predetermined characteristics of said data. When necessary, such data can be recovered using generated metadata associated with the data. Doing so, not only improves the storage efficiency of massively large genomic datasets, but also allows for the consistent reproduction of output data with the re-processing of intermediate data based on information stored in metadata.

Abstract: A method for efficiently processing and storing large data sets associated with a multi-stage bioinformatics analysis of genomic data is disclosed. The present method increases the efficiency of the electronic storage of these large data sets by automatically deleting or compressing intermediate data or a portion of output data and compressing input data, where both deletion and compression are based on predetermined characteristics of said data. When necessary, such data can be recovered using generated metadata associated with the data. Doing so, not only improves the storage efficiency of massively large genomic datasets, but also allows for the consistent reproduction of output data with the re-processing of intermediate data based on information stored in metadata.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: A method for efficiently processing and storing large data sets associated with a multi-stage bioinformatics analysis of genomic data is disclosed. The present method increases the efficiency of the electronic storage of these large data sets by automatically deleting or compressing intermediate data or a portion of output data and compressing input data, where both deletion and compression are based on predetermined characteristics of said data. When necessary, such data can be recovered using generated metadata associated with the data. Doing so, not only improves the storage efficiency of massively large genomic datasets, but also allows for the consistent reproduction of output data with the re-processing of intermediate data based on information stored in metadata.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask.

Abstract: A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Abstract: Illustrative embodiments of systems for characterizing resonance behavior of magnetostrictive resonators are disclosed. In one illustrative embodiment, an apparatus may comprise a first channel including one or more driving coils and one or more magnetostrictive resonators, the first channel having a first impedance; a second channel having a second impedance, the second impedance differing from the first impedance by an impedance attributable to the one or more magnetostrictive resonators; a signal source configured to apply an input signal to both the first and second channels; and a signal receiver configured to generate a combined output signal in response to output signals measured from both the first and second channels.

Abstract: In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask.

Abstract: Illustrative embodiments of systems for characterizing resonance behavior of magnetostrictive resonators are disclosed. In one illustrative embodiment, an apparatus may comprise a first channel including one or more driving coils and one or more magnetostrictive resonators, the first channel having a first impedance; a second channel having a second impedance, the second impedance differing from the first impedance by an impedance attributable to the one or more magnetostrictive resonators; a signal source configured to apply an input signal to both the first and second channels; and a signal receiver configured to generate a combined output signal in response to output signals measured from both the first and second channels.

Abstract: Included in the present disclosure are a system, method and program of instructions operable to protect vital information by combining information about a user and what they are allowed to see with information about essential files that need to be protected on an information handling system. Using intelligent security rules, essential information may be encrypted without encrypting the entire operating system or application files. According to aspects of the present disclosure, shared data, user data, temporary files, paging files, the password hash that is stored in the registry, and data stored on removable media may be protected.

Abstract: In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask.

Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.

Abstract: In one embodiment, a processor includes processing cores, and instruction stores storing instructions at least one instructions having a group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having group execution masks and a store execution matrix having store execution masks. The processor further includes a core selection unit that, for each instruction, selects a store execution mask using the unique identifier as an index. The core selection unit for each instruction, selects at least one group execution mask using the group number as an index, and performs logic operations on the selected group execution mask and the store execution mask to create a core request mask. The processor also includes an arbitration unit that determines instruction priority, assigns an instruction for each available core, and signals the instruction store of the assigned instruction to send the assigned instruction to the available core.

Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.