Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Abstract: A current switching system is described. This system includes first and second mirrored devices coupled to each other and a coupled terminal, and the first and second mirrored devices are coupled to an input terminal and an output terminal; a storage element in element in parallel with the first mirrored device and the first degeneration device; a variable impedance device coupled between the coupled terminal and a low voltage device; and a current mirroring accuracy enhancing circuit coupled between the coupled terminal and a high voltage device, wherein the variable impedance device dynamically changes a current at the coupled terminal to a second level depending when a threshold is met, and an impedance on the coupled terminal remains low both before switching and during switching.

Abstract: Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Abstract: Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer is in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Abstract: An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Abstract: The present invention discloses an apparatus (160) comprising a common mode generator circuit (162) coupled to a current directing circuit adapted to provide current to a first write head connection node (170) and to a second write head connection node (172).

Abstract: Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.

Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Abstract: A fly height controller (10FHC; 10FHC?) for controlling the fly height of a read/write head assembly (15) in a disk drive (20) is disclosed. A heat element resistor (30) is disposed within the read/write head assembly (15). The fly height controller (10FHC; 10FHC?) includes registers (32R, 32W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor (30) during read and write operations. The registers (32R, 32W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (36), depending upon whether a read or write operation is occurring; the output of the steady-state DAC (36) is applied to a voltage driver (40), which in turn drives current into the heat element resistor (30). Overdrive and underdrive transistors (44P, 44N) are provided to overdrive and underdrive the input to the voltage driver (40) in transitions between read and write operations.

Abstract: An apparatus for characterizing impedance presented to a write driver device in a write head assembly for use with an electromagnetic storage product includes: (a) a test impedance unit coupled with the write driver device; and (b) a measuring unit coupled with the test impedance unit. The measuring unit receives a measured parameter associated with the test impedance unit and compares the measured parameter with a reference parameter. The measuring unit indicates a result of the comparing.

Abstract: An apparatus for monitoring changes in a magnetic field using a magneto-resistive device situated in the field includes a first and second input locus coupled with the magneto-resistive device. An amplifier means for amplifying electrical signals has input terminals and output terminals. A first input terminal is coupled with the first input locus with a first capacitor coupled in series between the first input locus and the first input terminal. A second input terminal is coupled with the second input locus with a second capacitor coupled in series between the second input locus and the second input terminal. The apparatus receives a bias current at the first input locus that cooperates with the magneto-resistive element to affect electrical potential at the first input locus. The amplifier device presents at least one output signal at the output terminals indicating changes in the magnetic field.

Abstract: An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Abstract: An apparatus for use in applying write signals including a first and second write signal for a write head to write information to a memory device includes: (a) a current director for receiving the write signals and directing a write current to establish a write voltage across the write head in a first excursion in response to the first write signal and in a second excursion in response to the second write signal; the first and second excursions occurring about a common mode voltage; (b) a voltage drop unit coupled with a supply voltage and the current director at a connection locus for establishing the common mode voltage substantially equal with the supply voltage less a voltage drop; and (c) a switching unit coupled with the voltage drop unit and the connection locus and cooperating with the voltage drop unit to vary the voltage drop.

Abstract: The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system.

Abstract: A digital temperature monitor (DTM (24) includes a proportional-to-absolute temperature (PTAT) sensor (44) and reference circuit (48) coupled to the inputs of a comparator (42). The DTM (24) monitors the temperature of adjacent and/or proximate integrated circuitry. The method includes the steps of providing a reference signal to the comparator (42), increasing the reference signal voltage, and determining the temperature of an integrated circuit by determining when the reference signal is greater than the PTAT sensor (44) output voltage. The DTM (24) may be implemented as part of a hard-disk drive preamplifier circuit (22).

Abstract: A circuit (80) and method (84) for protecting read heads (18) of a hard-disk drive system (100). Capacitor C1 is controllably coupled to a dummy head Rdummy during a Vbias mode, so that capacitor C1 has a low, predictable voltage upon returning to Ibias mode, protecting the read heads (18) from damage. The circuit (80) includes logic (82) and algorithm (84) determining when to couple the capacitor C1 to the dummy head Rdummy during a servo bank write (SBW) sequence.

Abstract: A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.

Abstract: An active damping circuit including an H-bridge circuit having an inductive load and a switching circuit, an impedance circuit responsive to a bias signal to damp the H-bridge circuit, and a bias circuit to generate the bias signal responsive to the voltage drop across the H-bridge circuit.