Abstract: The present invention provides an apparatus, system and method of improving the bias response time for pre-amplifier circuits which utilize noise reduction capacitors 275. The system uses a quick recovery circuit 210 electrically connected to the capacitive node 216 of the pre-amplifier circuit. The quick recovery circuit 210 comprises a gain amplifier 218 with a resistive input and a controlled current source 219. The controlled current source corresponds to adjustments in a controlled current source 225 of the pre-amplifier and is electrically connected to the resistive input of the gain amplifier 218. The gain amplifier 218 can be selectively switched 211 to operatively connect an output to the capacitive node 216 of the pre-amplifier circuit.

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Abstract: A voltage to current conversion circuit is described. The circuit comprises a first differential amplifier for receiving an input voltage and producing an output voltage, and a second amplifier for converting the output voltage of the first amplifier to a current. The transfer function of the voltage to current conversion circuit is proportional to an exponential function that depends on the input voltage. The circuit is temperature and process independent. In a first preferred embodiment, the first amplifier comprises a first transistor for receiving an input voltage at its base terminal, a temperature dependent current source coupled to the emitter of the first transistor, and a positive voltage supply coupled to the collector through a diode coupled transistor, and a second transistor paired with the first transistor and having a base terminal coupled to an input voltage terminal, an emitter coupled to a temperature dependent current source, and a collector coupled to a voltage supply.

Abstract: Fixed gain amplifiers have particular use in the read channel of hard disk drives. A CMOS fixed gain amplifier 18c having a constant gain over the large dynamic range of hard disk drive applications is provided by incorporating super follower transistors M3 and M4 into the input stage of the fixed gain amplifier. The super follower transistors are folded into the output stage of the amplifier. The differential current through the degeneration resistor RE1 travels through the super follower transistors M3 and M4 and into the current mirrors I5 and I6. Thus the ac differential current goes directly to the cascoded stage, into the load resistors RL1 and RL2, and to the output load.

Abstract: The present invention provides an apparatus, system and method of improving the bias response time for pre-amplifier circuits which utilize noise reduction capacitors 275. The system uses a quick recovery circuit 210 electrically connected to the capacitive node 216 of the pre-amplifier circuit. The quick recovery circuit 210 comprises a gain amplifier 218 with a resistive input and a controlled current source 219. The controlled current source corresponds to adjustments in a controlled current source 225 of the preamplifier and is electrically connected to the resistive input of the gain amplifier 218. The gain amplifier 218 can be selectively switched 211 to operatively connect an output to the capacitive node 216 of the pre-amplifier circuit.

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Abstract: A hard disk drive system (10) includes a read/write head (21) for reading and writing data to and from a rotating magnetic disk (12). The read/write head includes a portion which is a magneto-resistive read head (36), the output of which is supplied through a preamplifier (26) to a read channel circuit (27). The read head has a nonlinear transfer function. The read channel circuit includes an asymmetry compensation circuit (62), which generates an analog compensation signal by squaring an output signal from the read head and scaling by an asymmetry factor (.alpha.'). The analog compensation signal is combined with the analog output signal in order to obtain a corrected analog signal, which is substantially free of the distortion introduced by the read head.

Abstract: An improved power-up circuit utilizing a simple current channel to rapidly charge or discharge nodes during the power-up transient, the time from when the circuit is signaled to power up to the time when the circuit becomes fully functional. The invention allows critical nodes previously limiting the power-up sequence to be rapidly charged to significantly improve the power-up performance of power savings circuits.