Abstract: According to one embodiment, a method, computer system, and computer program product for managing access to data is provided. The embodiment may include identifying one or more prefetch streams. The embodiment may also include saving a memory access instruction that created or advanced a selected prefetch stream from the one or more prefetch streams. The embodiment may further include detecting a pipeline flush prior to the saved memory access instruction. The embodiment may also include stopping the portion of the selected prefetch stream that follows the saved memory access instruction based on a type of the saved memory access instruction.

Abstract: A method includes receiving input frames of video information. An uplink channel receives a requirements indication from a mobile device configured to implement a diffusion model. Based upon the requirements indication, a current video coding modality is selected from among a first video coding modality and a second video coding modality where the first video coding modality utilizes diffusion, and the second video coding modality does not utilize diffusion. Video coding data is generated by processing the input frames of video information using the current video coding modality. The video coding data is sent to the mobile device.

Abstract: A computer-implemented method includes receiving at a first computing device a first machine-learned latent space model of a first scene located proximate a second computing device where the first scene includes a first face. The first machine-learned latent space model of the first scene is decoded to produce first generated imagery corresponding to the first scene from a first viewpoint defined by a first virtual camera. The first virtual camera is positioned in alignment with a display screen of the second computing device.

Abstract: A pioneering parallel diffusion technique individually represents and diffuses each bit or groups of bits. The approach addresses inefficiencies observed in traditional diffusion processes. The approach may reduce the number of iterations required for denoising, thereby decreasing denoising latency and improving overall processing speed. These advantages are especially crucial in the realm of codec applications where real-time processing and resource efficiency are paramount.

Abstract: A computer-implemented method includes generating a set of weights for a diffusion model. The generating includes reducing fidelity of training frames of training image data to create frames of reduced-fidelity training image data, encoding the frames of reduced-fidelity training image data to create frames of compressed reduced-fidelity training image data, and training a first artificial neural network using the frames of compressed reduced-fidelity training image data where values of the weights are adjusted during the training. The values of the weights are sent to a computing device configured to use the values of the weights to establish a second artificial neural network configured to substantially replicate the first artificial neural network.

Abstract: A computer-implemented method includes receiving training data with training images of a scene and associated camera extrinsics corresponding to three-dimensional (3D) camera locations and camera directions from which the training images are captured. Using the training data, a neural network is trained to represent a latent model of the scene in a latent space where the neural network is configured to synthesize scene images corresponding to novel views of the scene from queried 3D viewpoints and viewing angles. View spotlight information is received. The training of the neural network is prioritized based upon the view spotlight information.

Abstract: A computer-implemented method for generating image sequences includes receiving, at a computing device, values of a set of weights for a diffusion model. The weights are generated by training a first artificial neural network using training frames of training image data in combination with a first set of data derived from the frames of training image data. The values of the set of weights are adjusted during the training. A second artificial neural network present on the computing uses the values of the set of weights and receives a second set of data derived from frames of image data containing at least some scene information present in the training frames of training image data. The second set of data is provided to the second artificial neural network to implement the diffusion model. Images corresponding to the frames of image data are then generated by the second artificial neural network.

Abstract: A system and method generates 3D-aware reconstructions of a static or dynamic scene by using a neural network to encode captured images of the scene into a compact latent space scene model. The method includes receiving image frames of a scene where each image frame is associated with camera extrinsics including a three-dimensional (3D) camera location and a camera direction. A neural network is trained using the image frames (e.g., video frames) and the camera extrinsics to encode the frames as models of the scene in a latent space associated with a latent model decoder. The method further includes transmitting one or more of the models of the scene to a viewing device including the latent model decoder. The latent model decoder is configured to decode the models to generate imagery corresponding to novel 3D views of the scene.

Abstract: A system and method for generating 3D-aware reconstructions of a static or dynamic scene by using a neural network to encode captured images of the scene into a compact spatio-temporal polynomial latent space scene model. Image frames of a scene are received. Each image frame is associated with camera extrinsics including a three-dimensional (3D) camera location and a camera direction. A neural network is trained using the image frames (e.g., video frames) and the camera extrinsics to encode the frames as models of the scene in a spatio-temporal polynomial latent space. The models of the scene are transmitted to a viewing device including a latent model decoder. The latent model decoder is configured to decode the models to generate imagery corresponding to novel 3D views of the scene.

Abstract: Embodiments relate to sideband instruction address translation. According to an aspect, a computer-implemented method includes managing, within a processor, an instruction effective-to-real-address table (I-ERAT) separate from a main ERAT, where the I-ERAT has a smaller storage capacity than the main ERAT. The method also includes indicating an I-ERAT hit based on determining that an instruction address for an instruction cache is stored in the I-ERAT, bypassing an arbitrator within the processor and sending a translated address from the I-ERAT to the instruction cache based on detecting the I-ERAT hit, and sending an address translation request through the arbitrator to the main ERAT based on an I-ERAT miss and writing a translation result of the main ERAT to the I-ERAT.

Abstract: A computer system, processor, programming instructions and/or method for managing operations of a gather buffer for a processor core load storage unit. The processor core includes a processing pipeline having one or more execution units for processing unaligned load instructions that executes in two phases to satisfy. A buffer storage element is provided having a plurality of entries for temporarily collecting partial writeback results retrieved from the memory that are associated with first phase accesses for each of a plurality of unaligned load instructions. An associated logic controller device tracks two parts of the unaligned load to be gathered at independent times, wherein said partial result stored at said buffer storage element comprises a first part of an unaligned load. The second phase load access for the same instruction is independently accessed and later merged with first part of the load data at byte granularity to satisfy the load.

Abstract: A first instruction for processing by a processor core is received. Whether the instruction is a larx is determined. Responsive to determining the instruction is a larx, whether a cacheline associated with the larx is locked is determined. Responsive to determining the cacheline associated with the larx is not locked, the cacheline associated with the larx is locked and a counter associated with a first thread of the processor core is started. The first thread is processing the first instruction.

Abstract: The present disclosure is directed to the use of perlecan compositions to reduce the risk of mortality in subjects due to neurological injury such as stroke, including large vessel occlusion, and traumatic brain injury. The disclosure is also directed to the use of perlecan compositions to reduce mortality in stroke patients treated with tPA.

Abstract: A computer system, processor, programming instructions and/or method for managing operations of a gather buffer for a processor core load storage unit. The processor core includes a processing pipeline having one or more execution units for processing unaligned load instructions that executes in two phases to satisfy. A buffer storage element is provided having a plurality of entries for temporarily collecting partial writeback results retrieved from the memory that are associated with first phase accesses for each of a plurality of unaligned load instructions. An associated logic controller device tracks two parts of the unaligned load to be gathered at independent times, wherein said partial result stored at said buffer storage element comprises a first part of an unaligned load. The second phase load access for the same instruction is independently accessed and later merged with first part of the load data at byte granularity to satisfy the load.

Abstract: Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Abstract: A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.

Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to generate a first prefetch request and a second prefetch request based on the demand access stream, to output the first prefetch request to a first translation lookaside buffer (TLB), and to output the second prefetch request to a second TLB that is different from the first TLB. The processor performs a first TLB lookup in the first TLB based on one of the demand access stream or the first prefetch request, and performs a second TLB lookup in the second TLB based on the second prefetch request.

Abstract: A computer system, processor, programming instructions and/or method for managing operations of a gather buffer for a processor core load storage unit. The processor core includes a processing pipeline having one or more execution units for processing unaligned load instructions that executes in two phases to satisfy. A buffer storage element is provided having a plurality of entries for temporarily collecting partial writeback results retrieved from the memory that are associated with first phase accesses for each of a plurality of unaligned load instructions. An associated logic controller device tracks two parts of the unaligned load to be gathered at independent times, wherein said partial result stored at said buffer storage element comprises a first part of an unaligned load. The second phase load access for the same instruction is independently accessed and later merged with first part of the load data at byte granularity to satisfy the load.

Abstract: A first instruction for processing by a processor core is received. Whether the instruction is a larx is determined. Responsive to determining the instruction is a larx, whether a cacheline associated with the larx is locked is determined. Responsive to determining the cacheline associated with the larx is not locked, the cacheline associated with the larx is locked and a counter associated with a first thread of the processor core is started. The first thread is processing the first instruction.