Abstract: A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.

Abstract: Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.

Abstract: A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.

Abstract: A computer system, processor, and/or load-store unit has a data cache for storing data, the data cache having a plurality of entries to store the data, each data cache entry addressed by a row and a Way, each data cache row having a plurality of the data cache Ways; a first Address Directory organized and arranged the same as the data cache where each first Address Directory entry is addressed by a row and a Way where each row has a plurality of Ways; a store reorder queue for tracking the store instructions; and a load reorder queue for tracking load instruction. Each of the load and store reorder queues having a Way bit field, preferably less than six bits, for identifying the data cache Way and/or a first Address Directory Way where the Way bit field acts as a proxy for a larger address, e.g. a real page number.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: A computer system, includes a store queue that holds store entries and a load queue that holds load entries sleeping on a store entry. A processor detects a store drain merge operation call and generates a pair of store tags comprising a first store tag corresponding to a first store entry to be drained and a second store tag corresponding to a second store entry to be drained. The processor determines the pair of store tags an even-type store tag or an odd-type store tag. The processor disables the odd store tag included in the even-type store tag pair when detecting the even-type store tag pair, and wakes up a first load entry dependent on the even store tag and a second load entry dependent on the odd store tag based on the even store tag included in the even-type store tag pair while the odd store tag is disabled.

Abstract: Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.

Abstract: Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Abstract: System includes at least one computer processor having a load store execution unit (LSU) for processing load and store instructions, wherein the LSU includes (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a width for storing the data; and (b) a gather buffer for holding data, wherein the processor is configured to: process oversize data larger than the width of the data field of the store queue, and process an oversize load instruction for oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data.

Abstract: Provided is a method for fusing store instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of a microprocessor. The method further includes determining that the two instructions meet a fusion criteria. In response to determining that the two instructions meet the fusion criteria, the two instructions are recoded into a fused instruction. The fused instruction is executed.

Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.

Abstract: Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.

Abstract: In at least one embodiment, a processing unit includes a processor core and a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache. The upper-level cache includes a data array and an effective address (EA) directory. The processor core includes an execution unit, an address translation unit, and a prefetch unit configured to initiate allocation of a directory entry in the EA directory for a store target EA without prefetching a cache line of data into the corresponding data entry in the data array. The processor core caches in the directory entry an EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation by the translation unit.

Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: A system of handling electronic information having a virtually tagged cache having a directory and a plurality of entries containing data, the directory containing multiple entries, each entry configured to comprise at least a virtual address and one of a plurality of context tags, wherein each context tag is an encoding for one of a plurality of layers of address space; a context tag table having a plurality of entries, each entry configured to map one of the plurality of context tags to one of the plurality of layers of space; and a scratch register containing a current context tag for a current layer of address space on which the processor is operating. The virtually tagged cache is configured to preserve information in the virtually tagged cache when performing a context switch in the system.

Abstract: A system and method of handling data access demands in a processor virtual cache that includes: determining if a virtual cache data access demand missed because of a difference in the context tag of the data access demand and a corresponding entry in the virtual cache with the same virtual address as the data access demand; in response to the virtual cache missing, determining whether the alias tag valid bit is set in the corresponding entry of the virtual cache; in response to the alias tag valid bit not being set, determining whether the virtual cache data access demand is a synonym of the corresponding entry in the virtual cache; and in response to the virtual access demand being a synonym of the corresponding entry in the virtual cache with the same virtual address but a different context tag, updating information in a tagged entry in an alias table.

Abstract: A system and method of stopping program execution includes tagging an entry in a virtual cache with an indicator bit where the virtual address of the entry corresponds to a virtual address range in a break point register, in response to a second virtual cache data access demand matching the entry tagged with the indicator bit, determining whether the second data access demand matches the virtual address range of the breakpoint register, and in response to the second data access demand matching the virtual address range of the break point register, flagging an exception and stopping execution of the program. In an embodiment, the method or system enters a slow-mode in response to the second data access demand matching the virtual cache entry with the indicator bit, and performs a full comparison between the second data access demand and the break point register virtual address range.

Abstract: A system and method of handling access demands in a virtual cache comprising, by a processing system, checking if a virtual cache access demand missed because of a synonym tagged in the virtual cache; in response to the virtual cache access demand missing because of a synonym tagged in the virtual cache, updating the virtual address tag in the virtual cache to a new virtual address tag; searching for additional synonyms tagged in the virtual cache; and in response to finding additional synonyms tagged in the virtual cache, updating the virtual address tag of the additional synonyms to the new virtual address tag.

Abstract: A system and method of handling access demands in a virtual cache comprising, by a processing system, checking if a virtual cache access demand missed because of a synonym tagged in the virtual cache; in response to the virtual cache access demand missing because of a synonym tagged in the virtual cache, updating the virtual address tag in the virtual cache to a new virtual address tag; searching for additional synonyms tagged in the virtual cache; and in response to finding additional synonyms tagged in the virtual cache, updating the virtual address tag of the additional synonyms to the new virtual address tag.