Patents by Inventor Bryan Sheffield
Bryan Sheffield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9419617Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.Type: GrantFiled: July 15, 2014Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
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Publication number: 20140320169Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.Type: ApplicationFiled: July 15, 2014Publication date: October 30, 2014Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
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Patent number: 8791720Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.Type: GrantFiled: October 3, 2013Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
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Publication number: 20140028350Abstract: A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode.Type: ApplicationFiled: October 3, 2013Publication date: January 30, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
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Patent number: 8570068Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.Type: GrantFiled: April 28, 2010Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
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Publication number: 20120324413Abstract: A method includes simulating a first design of a semiconductor memory that includes at least one device disposed between and coupled to a memory bit cell and to a power supply line, determining if at least one simulated operational value of the semiconductor memory is above a threshold value, and adjusting at least one of a size of the device or a type of the device if the at least one simulated operational value is below the threshold value. The memory bit cell is disposed in a column including a plurality of bit cells. The size or type of the device is repeatedly adjusted and the design of the semiconductor memory is repeatedly simulated until the at least one simulated operational value is at or above the threshold value.Type: ApplicationFiled: January 31, 2012Publication date: December 20, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Bryan SHEFFIELD
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Patent number: 8093716Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.Type: GrantFiled: July 29, 2005Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Robert L. Pitts, Bryan Sheffield, Roger Griesmer, Joe McPherson
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Publication number: 20110267107Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.Type: ApplicationFiled: April 28, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Ming-Chieh HUANG, Bryan SHEFFIELD, Chih-Chang LIN
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Patent number: 7376871Abstract: Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.Type: GrantFiled: August 6, 2003Date of Patent: May 20, 2008Assignee: Texas Instruments IncorporatedInventors: George Ernest Harris, Bryan Sheffield, Dwayne Ward
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Patent number: 7230868Abstract: An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.Type: GrantFiled: July 28, 2005Date of Patent: June 12, 2007Assignee: Texas Instruments IncorporatedInventors: Sudhir K. Madan, Bryan Sheffield
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Publication number: 20070081379Abstract: One embodiment provides a system to assist setting a state of a latch system. The system includes a latch system connected to a node, the latch system residing in one of a first state and a second state. A charge storage device is coupled to maintain the node at a first voltage according to an amount of stored charge. A write assist system is connected between the node and a second voltage. The write assist network is configured, when the node is selected, to discharge the charge storage device and to pull the node from the first voltage to a discharge voltage that is outside a range defined by the first voltage and the second voltage to facilitate setting the latch system to another of the first state and the second state.Type: ApplicationFiled: September 23, 2005Publication date: April 12, 2007Inventors: Michael Clinton, Stephen Heinrich-Barna, Theodore Houston, George Jamison, Kun-hsi Li, Jonathon Miller, Bryan Sheffield
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Publication number: 20070036012Abstract: An amplifier circuit and method is disclosed. The amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706,708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726). The control gates of the first and second pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.Type: ApplicationFiled: July 28, 2005Publication date: February 15, 2007Inventors: Sudhir Madan, Bryan Sheffield
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Publication number: 20070023859Abstract: The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Applicant: Texas Instruments IncorporatedInventors: Robert Pitts, Bryan Sheffield, Roger Griesmer, Joe McPherson
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Patent number: 7095671Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: GrantFiled: May 3, 2005Date of Patent: August 22, 2006Assignee: Texas Instruments IncorporatedInventors: Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan Le, Sanjive Agarwala
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Publication number: 20060171239Abstract: A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).Type: ApplicationFiled: February 2, 2005Publication date: August 3, 2006Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Suresh BALASUBRAMANIAN, Lakshmikantha HOLLA, Bryan SHEFFIELD
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Publication number: 20050247995Abstract: Severable metal contacts (42) are provided for use within a circuit in a semiconductor device whereby an open circuit may be formed by the application of a pre-selected voltage or current. Preferred embodiments and associated methods are described in which a semiconductor device fuse (30) includes first and second conductors (36, 38) having first and second metallic contacts (40, 42) operably coupled to a conductive layer (34) for forming an electrical path. At least one of the metallic contacts (42) is configured to operate as a metallic fuse element adapted to form an open circuit (44) in response to reaching a pre-selected voltage threshold or current. Preferred embodiments of the invention are described in which it is used for programmable read only memory (PROM) elements.Type: ApplicationFiled: May 6, 2004Publication date: November 10, 2005Inventors: Robert Pitts, Bryan Sheffield, Roger Greismer
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Publication number: 20050213411Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: ApplicationFiled: May 3, 2005Publication date: September 29, 2005Inventors: Manjeri Krishnan, Bryan Sheffield, Joel Graber, Duy-Loan Le, Sanjive Agarwala
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Patent number: 6928011Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: GrantFiled: July 30, 2003Date of Patent: August 9, 2005Assignee: Texas Instruments IncorporatedInventors: Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan Le, Sanjive Agarwala
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Publication number: 20050169078Abstract: An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.Type: ApplicationFiled: February 2, 2004Publication date: August 4, 2005Applicant: Texas Instruments IncorporatedInventors: Suresh Balasubramanian, Stephen Spriggs, Bryan Sheffield, Mohan Mishra
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Publication number: 20050169077Abstract: A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.Type: ApplicationFiled: February 2, 2004Publication date: August 4, 2005Applicant: Texas Instruments IncorporatedInventors: Suresh Balasubramanian, Stephen Spriggs, Bryan Sheffield, Mohan Mishra