Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: Methods of forming a contact pad include forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of an upper surface of the copper pattern. A diffusion barrier layer is formed in the opening by electroless plating the diffusion barrier layer onto the exposed portion of the upper surface of the copper pattern. This diffusion barrier layer operates as a barrier to copper out-diffusion from the copper pattern. These methods further include conformally depositing an underbump metallization layer onto at least a sidewall of the opening in the passivation layer and onto an upper surface of the diffusion barrier layer. A step is then performed to plate a contact bump (e.g., solder bump) onto a portion of the underbump metallization layer extending opposite the diffusion barrier layer.

Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or less.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: A plasma vapor deposition system is described for forming a feature on a semiconductor wafer. The plasma vapor deposition comprises a primary target electrode and a plurality of secondary target electrodes. The deposition is performed by sputtering atoms off the primary and secondary target electrodes.

Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.

Abstract: A sputtering apparatus includes a target electrode and a bias source electrically coupled to the target electrode. A wafer chuck is spaced from the target electrode. The wafer chuck is partitioned into a plurality of zones, each zone being coupled to receive an AC signal having an amplitude that can vary by zone. At least one RF coil is positioned adjacent a space between the target electrode and the wafer chuck.

Abstract: Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over a semiconductive material. The device is heated, causing atoms of the semiconductive material to move towards and bond to the atoms of the second metal, leaving vacancies in the semiconductive material, and causing atoms of the first metal to move into the vacancies in the semiconductive material.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, and an electrode structure which is formed on the conductive plug.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.

Abstract: Methods of forming barrier layers and structures thereof are disclosed. A nitrogen rich region is formed at a top surface of a barrier layer by exposing the barrier layer to a nitridation treatment. The nitrogen rich region increases the oxidation resistance of the barrier layer. The barrier layers have improved diffusion barrier properties. A stack of barrier layers may be formed, with one or more of the barrier layers in the stack being exposed to a nitridation treatment.

Abstract: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or more.

Abstract: A ferroelectric capacitor in which damage caused by etching exposed faces of a ferroelectric layer of the capacitor is compensated by depositing a seeding layer of ferroelectric material such as PZT on one or more exposed faces of the ferroelectric layer and depositing an electrode layer made of conductive material such as platinum on the seeding layer. An oxygen annealing recovery process is applied to the device. The seeding layer can transform the phase of the damaged surfaces from amorphous to crystalline during the recovery annealing process and, at the same time, provide the damaged surfaces of the ferroelectric layer with missing element(s), for example lead. The oxygen necessary for recovery of the damage may be obtained through the platinum layer from the oxygen atmosphere.

Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, and an electrode structure which is formed on the conductive plug.