Abstract: A power module includes a lead frame, a substrate mounted on the lead frame, a first anchor pad, a second anchor pad, a plurality of die pads, and a plurality of transistor dies. The lead frame includes a first lead frame anchored bar attached to the first anchor pad, and a second lead frame anchored bar attached to the second anchor pad. The power module may include a single control IC or two or more control ICs. For the case including a single control IC, the singe control IC controls a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. For the case including two control ICs, a low voltage IC controls a first transistor, a second transistor, and a third transistor and the high voltage IC controls a fourth transistor, a fifth transistor, and a sixth transistor.

Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

Abstract: An intelligent power module (IPM) comprises a first transistor die supporting element, a second transistor die supporting element, a third transistor die supporting element, and a fourth transistor die supporting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a tie bar, a low voltage IC, a high voltage IC, a plurality of leads, a first slanted section, a second slanted section, a third slanted section, a fourth slanted section, a fifth slanted section, and a molding encapsulation. A respective bottom surface of each of the first, second, third, and fourth transistor die supporting elements are exposed from the molding encapsulation.

Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.

Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

Abstract: A method of generating a gate drive signal for driving a control terminal of a power switch includes detecting a system input signal; determining a signal pulse of the system input signal being a first signal pulse following a power up event, or following an idle period, or following removal of a fault condition; and in response, generating a soft gate drive signal to drive the control terminal of the power switch to softly turn on the power switch. In another embodiment, the method includes determining a duration of the on period of the system input signal exceeding a maximum on duration and in response, disabling the gate drive signal to turn off the power switch; and determining a deassertion transition of the system input signal and in response, blocking the system input signal from the gate drive signal for a minimum off duration.

Abstract: An interconnected base plate comprises a metal layer, a plurality of metal pads, and a molding encapsulation. The mold compound layer encloses a majority portion of the plurality of metal pads 240. A respective top surface of each of the plurality of metal pads is exposed from a top surface of the molding encapsulation. The respective top surface of said each of the first plurality of metal pads and the top surface of the mold compound layer are co-planar. A power module comprises the interconnected base plate, a plurality of chips, a plurality of bonding wires, a plurality of terminals, a plastic case, and a module-level molding encapsulation. A method, for fabricating an interconnected base plate, comprises the steps of forming a plurality of metal pads; loading a metal layer; forming a molding encapsulation; and applying a singulation process.

Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.

Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.

Abstract: An apparatus comprising an insulated gate bipolar transistor; and a super-junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor wherein the super-junction metal-oxide semiconductor field effect transistor are structurally coupled and wherein the super-junction metal-oxide semiconductor field effect transistor is configured to switch to an ‘on’ state from an ‘off’ state and an ‘off’ state from an ‘on’ state.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.

Abstract: A method of generating a gate drive signal for driving a control terminal of a power switch includes detecting a system input signal; determining a signal pulse of the system input signal being a first signal pulse following a power up event, or following an idle period, or following removal of a fault condition; and in response, generating a soft gate drive signal to drive the control terminal of the power switch to softly turn on the power switch. In another embodiment, the method includes determining a duration of the on period of the system input signal exceeding a maximum on duration and in response, disabling the gate drive signal to turn off the power switch; and determining a deassertion transition of the system input signal and in response, blocking the system input signal from the gate drive signal for a minimum off duration.

Abstract: A controller for driving a power switch incorporates a hard turn-on disable circuit to prevent the power switch from turning on when the power switch is sustaining a high voltage value. The hard turn-on disable circuit includes a hard turn-on detection circuit and a protection logic circuit. The hard turn-on disable circuit is configured to block or to pass the system input signal to the normal gate drive circuit of the power switch depending on the detection indicator signal. In particular, the protection logic circuit blocks the system input signal VIN in response to a high voltage detection so that the power switch ignores the system input signal VIN, which may be erroneous, and the power switch is prevented from undesirable hard switching.

Abstract: An intelligent power module includes a power switch, a freewheeling device, and a controller circuit incorporating a gate drive circuit and one or more power switch protection circuits. In one embodiment, the power switch is an insulated gate bipolar transistor (IGBT) device, the freewheeling device is a PN junction diode, and the controller circuit is implemented as a semiconductor integrated circuit (IC). The power module implements protection functions for the power switching device where the protection circuits are formed on the controller circuit IC and co-packaged with the power switch. In some embodiments, the control circuit in the power module includes an active soft-start circuit which is activated to realize soft-start of the power switch. In other embodiments, the control circuit in the power module includes an active turn-on pulse control circuit to detect for abnormal system input signal pulse events and block system undesired input pulses.

Abstract: A controller for driving a power switch incorporates a protection circuit to protect the power switch from fault conditions, such as over-voltage conditions or power surge events. The protection circuit includes a fault detection circuit and a protection gate drive circuit. The fault detection circuit is configured to monitor the voltage across the power switch and to generate a fault detection indicator signal and the protection gate drive circuit is configured to generate a gate drive signal to turn on the power switch in response to a detected fault condition. In particular, the protection gate drive circuit generates a gate drive signal that has a slow assertion transition and is clamped at a given gate voltage value. In this manner, the protection circuit implements active clamping of the gate terminal of the power switch and safe handling of the power switch during over-voltage events.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.