Patents by Inventor Bungo Tanaka

Bungo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070145416
    Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Ohta, Bungo Tanaka
  • Publication number: 20060197146
    Abstract: A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type is formed in the base region. A drain region of the second conduction type is formed apart from the source region in the semiconductor layer. A gate electrode is formed on a gate insulator above the semiconductor layer between the source region and the drain region. A first interlayer insulator is formed on the semiconductor layer to cover the gate electrode. A short electrode is formed to short the base region and the source region. A second interlayer insulator is formed to cover the first interlayer insulator and the short electrode.
    Type: Application
    Filed: April 27, 2005
    Publication date: September 7, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 7045856
    Abstract: In a semiconductor layer of the first conductivity type, a first diffusion region of the second conductivity type is formed which includes a low resistance layer and a high resistance layer. This semiconductor layer of the first conductivity type has its thickness that is less than or equal to the lateral width of the high resistance layer.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 7019361
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20050258478
    Abstract: In a semiconductor layer of the first conductivity type, a first diffusion region of the second conductivity type is formed which includes a low resistance layer and a high resistance layer. This semiconductor layer of the first conductivity type has its thickness that is less than or equal to the lateral width of the high resistance layer.
    Type: Application
    Filed: July 19, 2004
    Publication date: November 24, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 6958514
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20050121718
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Application
    Filed: January 19, 2005
    Publication date: June 9, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20040046202
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Application
    Filed: April 3, 2003
    Publication date: March 11, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Patent number: 6690061
    Abstract: The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Yoneda, Bungo Tanaka
  • Publication number: 20030057503
    Abstract: The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.
    Type: Application
    Filed: September 25, 2002
    Publication date: March 27, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Yoneda, Bungo Tanaka