Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: A processing chamber is disclosed for planarizing material layers (for example, polymer layers). An exemplary processing chamber includes a substrate table configured to support a substrate having a material layer formed thereover and a flattening structure having a substantially flat surface. The flattening structure moves freely with respect to a non-uniform surface of the material layer, such that the non-uniform surface is flattened as the substantially flat surface contacts the non-uniform surface. In some implementations, the processing chamber further includes a pressing mechanism operatively coupled to the flattening structure, and a pivotal interface coupling the flattening structure to the pressing mechanism. The pressing mechanism presses the substantially flat surface of the flattening structure to the non-uniform surface of the material layer, and the pivotal interface allows the flattening structure to pivot with respect to the pressing mechanism and with respect to the substrate.

Abstract: A charged particle multi-beam lithography system includes an illumination sub-system that is configured to generate a charged particle beam; and multiple plates with a first aperture through the plates. The plates and the first aperture are configured to form a charged particle doublet. The system further includes a blanker having a second aperture whose footprint is smaller than that of the first aperture. The charged particle doublet is configured to demagnify a portion of the charged particle beam passing through the first aperture, thereby producing a demagnified beamlet. The blanker is configured to receive the demagnified beamlet from the charged particle doublet, and is further configured to conditionally allow the demagnified beamlet to travel along a desired path.

Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.