Patents by Inventor Byeong-In Choe

Byeong-In Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8315103
    Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byeong-In Choe
  • Publication number: 20120230103
    Abstract: According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.
    Type: Application
    Filed: November 4, 2011
    Publication date: September 13, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeong-In Choe, Changseok Kang, Woonkyung Lee
  • Publication number: 20120195125
    Abstract: Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
    Type: Application
    Filed: December 9, 2011
    Publication date: August 2, 2012
    Inventors: BYEONG-IN CHOE, Sunil Shim, Woonkyung Lee, Jaehoon Jang
  • Publication number: 20120140562
    Abstract: A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byeong-In Choe, Sunil Shim, Sung-Hwan Jang, Woonkyung Lee, Jaehoon Jang
  • Publication number: 20120120732
    Abstract: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 17, 2012
    Inventors: Changhyun Lee, Jungdal Choi, Byeong-In Choe
  • Publication number: 20120098048
    Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.
    Type: Application
    Filed: August 30, 2011
    Publication date: April 26, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byeong-In CHOE, Jae-Hoon JANG, Sun-Il SHIM, Han-Soo KIM, Jin-Man HAN
  • Publication number: 20120081959
    Abstract: Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 5, 2012
    Inventors: Changhyun Lee, Jungdal Choi, Byeong-In Choe
  • Publication number: 20120033503
    Abstract: An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.
    Type: Application
    Filed: July 6, 2011
    Publication date: February 9, 2012
    Inventors: JUHYUNG KIM, Changseok Kang, Hansoo Kim, Byeong-In Choe
  • Publication number: 20120003828
    Abstract: A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Inventors: Sung-Il Chang, Changseok Kang, Byeong-In Choe
  • Publication number: 20110305079
    Abstract: A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Park, Changseok Kang, Sung-Il Chang, Byeong-In Choe
  • Publication number: 20110298037
    Abstract: A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 8, 2011
    Inventors: BYEONG-IN CHOE, SUNG-IL CHANG, CHANG-SEOK KANG, JIN-SOO LIM
  • Publication number: 20110286274
    Abstract: A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 24, 2011
    Inventors: Sung-Il Chang, Changseok Kang, Chan Park, Byeong-In Choe
  • Patent number: 8059466
    Abstract: Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Jungdal Choi, Byeong-In Choe
  • Publication number: 20110222340
    Abstract: Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 15, 2011
    Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byeong-In Choe
  • Publication number: 20110205802
    Abstract: Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 25, 2011
    Inventors: Byeong-In CHOE, Sung-Il Chang, Changseok Kang
  • Publication number: 20110079838
    Abstract: A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
    Type: Application
    Filed: December 7, 2010
    Publication date: April 7, 2011
    Inventors: Chang-Hyun Lee, Jung-Dal Choi, Chang-Seok Kang, Jin-Taek Park, Byeong-In Choe
  • Patent number: 7867883
    Abstract: A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Jung-Dal Choi, Chang-Seok Kang, Jin-Taek Park, Byeong-In Choe
  • Patent number: 7812375
    Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Tea-Kwang Yu, Jong-Sun Sel, Ju-Hyung Kim, Byeong-In Choe
  • Publication number: 20100214844
    Abstract: Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.
    Type: Application
    Filed: January 15, 2010
    Publication date: August 26, 2010
    Inventors: Changhyun Lee, Jungdal Choi, Byeong-In Choe
  • Publication number: 20090001451
    Abstract: A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Chang-Hyun Lee, Jung-Dal Choi, Chang-Seok Kang, Jin-Taek Park, Byeong-In Choe