Patents by Inventor Byeong-In Choe

Byeong-In Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070272971
    Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
    Type: Application
    Filed: April 12, 2007
    Publication date: November 29, 2007
    Inventors: Chang-Hyun Lee, Tea-Kwang Yu, Jong-Sun Sel, Ju-Hyung Kim, Byeong-In Choe