Abstract: A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a sidewall damaged by the etching remove a sacrificial silicon oxide layer. The example method also deposits a high-K dielectric as a gate dielectric, deposits a metal layer, planarizes the metal layer to a height of a hard oxide, forms a nitride layer on the planarized metal layer, and patterns the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern. Additionally, the example method forms a metal gate using the nitride layer pattern, removes a remaining hard oxide mask, and grows a sidewall oxide layer on the metal gate.

Abstract: A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.

Abstract: The present invention relates to a combined toaster and microwave oven that can obtain uniformly toasted slices of bread even when the slices of the bread are toasted successively several times. The combined toaster and microwave oven includes a key input unit for selecting user's favorite kind of the bread and baking level, a memory for storing heating time of the heaters according to the favorite kind of the bread and the favorite baking level, a temperature sensor for sensing internal temperature of the toaster, a controller for counting an elapsed time for the heaters to operate after the heaters stop and adjusting the heating time of the heaters according to the counted time and the internal temperature of the sensor.

Abstract: Disclosed are a cloned pig expressing green fluorescent protein (GFP) and a cloned pig having a 1,3-galactosyltransferase (GT) gene knocked out. Also, the present invention discloses methods of producing such cloned pigs, comprising the steps of establishing a somatic cell line; preparing a GFP-transfected or GT gene knock-out nuclear donor cell; producing a transgenic nuclear transfer embryo using the nuclear donor cell and a recipient oocyte; and transplanting the transgenic nuclear transfer embryo into a surrogate mother pig. The cloned pig expressing GFP of the present invention is useful for large-scale production of an animal disease model, and the GT gene knock-out cloned pig can be used as a organ donor allowing xenotransplantation in humans without hyperacute immune rejection.

Abstract: Toaster cum microwave oven having a heater for toasting bread, including a memory for storing a voltage level to a heater according to the function of the toaster the user selects, a temperature sensor for sensing an inside temperature of the toaster, and a microcomputer for controlling a toasting time period according to a kind and a toasting level of bread the user selects, and an inside temperature of the toaster, and controlling the microwave oven according to a command received through the first key input part, thereby permitting toasting bread to a desired degree of toasting regardless of the inside temperature and continued user of the toaster.

Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.