Patents by Inventor Byeong-Chan Lee
Byeong-Chan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250240994Abstract: Methods of manufacturing logic or memory devices are provided. The method includes selectively depositing a silicon-containing dielectric layer in a source/drain recess on a substrate and through an opening in an oxide liner within the source drain recess. The silicon-containing dielectric layer is then densified.Type: ApplicationFiled: December 12, 2024Publication date: July 24, 2025Applicant: Applied Materials, Inc.Inventors: Kyoung Ha Kim, Byeong Chan Lee, Veeraraghavan S. Basker, Naomi Yoshida
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Patent number: 12327761Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.Type: GrantFiled: April 25, 2022Date of Patent: June 10, 2025Assignee: APPLIED MATERIALS, INC.Inventors: Nicolas Louis Breil, Byeong Chan Lee, Benjamin Colombeau
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Patent number: 12284803Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.Type: GrantFiled: March 7, 2022Date of Patent: April 22, 2025Assignee: APPLIED MATERIALS, INC.Inventors: Nicolas Louis Breil, Fredrick Fishburn, Byeong Chan Lee
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Publication number: 20250063797Abstract: A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.Type: ApplicationFiled: July 2, 2024Publication date: February 20, 2025Inventors: Kyoung Ha KIM, Veeraraghavan S. BASKER, Byeong Chan LEE, Andrew YEOH
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Publication number: 20240379438Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.Type: ApplicationFiled: May 2, 2024Publication date: November 14, 2024Applicant: Applied Materials, Inc.Inventors: Veeraraghavan S. Basker, Kyoung Ha Kim, Byeong Chan Lee
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Publication number: 20240332388Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.Type: ApplicationFiled: March 19, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Byeong Chan Lee, Benjamin Colombeau, Nicolas Breil, Ashish Pal, El Mehdi Bazizi, Veeraraghavan S. Basker, Balasubramanian Pranatharthiharan, Pratik B. Vyas, Gregory Costrini
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Publication number: 20240321584Abstract: Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example, selective oxidation protects growth of silicon germanium (SiGe) layers on the sidewall of a superlattice structure during bottom-up epitaxial growth.Type: ApplicationFiled: March 13, 2024Publication date: September 26, 2024Applicant: Applied Materials, Inc.Inventors: Byeong Chan Lee, Benjamin Colombeau, Edy Cardona, Christopher S. Olsen, Shawn Thomas
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Publication number: 20240234544Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.Type: ApplicationFiled: December 13, 2023Publication date: July 11, 2024Applicant: Applied Materials, Inc.Inventors: Sai Hooi Yeong, Benjamin Colombeau, Liu Jiang, El Mehdi Bazizi, Byeong Chan Lee, Balasubramanian Pranatharthiharan
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Publication number: 20240128355Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent to a superlattice structure on a substrate. The source region and the drain region comprise a metallic silicide material. In some embodiments, a sacrificial material is first deposited and then removed to form a metallic silicide material in the source and drain region.Type: ApplicationFiled: October 11, 2023Publication date: April 18, 2024Applicant: Applied Materials, Inc.Inventors: Nicolas Breil, Byeong Chan Lee
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Patent number: 11923441Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20230307506Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source/drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400° C. The method may be performed in a processing chamber without breaking vacuum.Type: ApplicationFiled: March 15, 2023Publication date: September 28, 2023Applicant: Applied Materials, Inc.Inventors: Nicolas Breil, Matthew Cogorno, Anchuan Wang, Byeong Chan Lee, Manoj Vellaikal
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Publication number: 20220399457Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: August 16, 2022Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220384258Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.Type: ApplicationFiled: April 25, 2022Publication date: December 1, 2022Inventors: Nicolas Louis BREIL, Byeong Chan LEE, Benjamin COLOMBEAU
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Publication number: 20220336469Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.Type: ApplicationFiled: March 7, 2022Publication date: October 20, 2022Inventors: Nicolas Louis BREIL, Fredrick FISHBURN, Byeong Chan LEE
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Patent number: 11450759Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: September 30, 2020Date of Patent: September 20, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220254647Abstract: A semiconductor structure may include a source, a drain, a plurality of nanowire channels between the source and the drain, and a bottom insulation layer. The plurality of nanowire channels may each have a width defined by the source and drain. The bottom insulation layer may contact a bottom nanowire channel of the plurality of nanowire channels and may be disposed between the source and drain. The bottom insulation layer may have a width no greater than the width of the bottom nanowire channel.Type: ApplicationFiled: April 28, 2022Publication date: August 11, 2022Applicant: Applied Materials, Inc.Inventor: Byeong Chan Lee
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Patent number: 11348803Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.Type: GrantFiled: April 16, 2020Date of Patent: May 31, 2022Assignee: Applied Materials, Inc.Inventor: Byeong Chan Lee
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Patent number: 11189710Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.Type: GrantFiled: May 15, 2020Date of Patent: November 30, 2021Assignee: Applied Materials, Inc.Inventors: Byeong Chan Lee, Tejinder Singh, Bencherki Mebarki
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Publication number: 20210104617Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: September 30, 2020Publication date: April 8, 2021Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Patent number: 10969129Abstract: The disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). A method of a server is provided. The method includes determining a target temperature range to be applied to a first zone; predicting an indoor temperature for each of a plurality of zones included in a second zone in which the first zone is included; predicting efficiency of at least one first outdoor unit connected to first indoor units installed at the second zone; and controlling operations of the first indoor units based on the target temperature range, the indoor temperature for each of the plurality of zones, and the efficiency of at least one first outdoor unit.Type: GrantFiled: May 30, 2018Date of Patent: April 6, 2021Inventors: Kyung-Jae Kim, Kwan-Woo Song, Byeong-Chan Lee, Woon-Sik Lee, Je-Hyeon Lee, Hye-Jung Cho, Soon-Heum Ko, Sung-Geun Song, Jae-Hong Kim