Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent to a superlattice structure on a substrate. The source region and the drain region comprise a metallic silicide material. In some embodiments, a sacrificial material is first deposited and then removed to form a metallic silicide material in the source and drain region.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source/drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400° C. The method may be performed in a processing chamber without breaking vacuum.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Abstract: The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: A semiconductor structure may include a source, a drain, a plurality of nanowire channels between the source and the drain, and a bottom insulation layer. The plurality of nanowire channels may each have a width defined by the source and drain. The bottom insulation layer may contact a bottom nanowire channel of the plurality of nanowire channels and may be disposed between the source and drain. The bottom insulation layer may have a width no greater than the width of the bottom nanowire channel.

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Abstract: The disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). A method of a server is provided. The method includes determining a target temperature range to be applied to a first zone; predicting an indoor temperature for each of a plurality of zones included in a second zone in which the first zone is included; predicting efficiency of at least one first outdoor unit connected to first indoor units installed at the second zone; and controlling operations of the first indoor units based on the target temperature range, the indoor temperature for each of the plurality of zones, and the efficiency of at least one first outdoor unit.

Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

Abstract: Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

Abstract: Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Abstract: The disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). A method of a server is provided. The method includes determining a target temperature range to be applied to a first zone; predicting an indoor temperature for each of a plurality of zones included in a second zone in which the first zone is included; predicting efficiency of at least one first outdoor unit connected to first indoor units installed at the second zone; and controlling operations of the first indoor units based on the target temperature range, the indoor temperature for each of the plurality of zones, and the efficiency of at least one first outdoor unit.