Patents by Inventor Byong-man Kim

Byong-man Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030053399
    Abstract: A high-density information storage apparatus using electron emission and methods of writing, reading and erasing information using the same are provided. The high-density information storage apparatus includes a lower electrode, a photoconductive layer and a recording medium sequentially provided on the lower electrode, a conductive layer converting unit for making the photoconductive layer conductive, a data write and read unit for writing data to the recording medium or reading data from the recording medium, a data loss preventing unit for preventing loss of data during data write and read operations, and a power supply connected to the lower electrode and the data write and read unit, for supplying voltage necessary for reading and writing data.
    Type: Application
    Filed: March 6, 2002
    Publication date: March 20, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Won-bong Choi, Byong-man Kim
  • Publication number: 20020167002
    Abstract: A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.
    Type: Application
    Filed: April 19, 2002
    Publication date: November 14, 2002
    Inventors: Soo-Doo Chae, Byong-Man Kim, Moon-Kyung Kim, Hee-Soon Chae, Won-Il Ryu
  • Publication number: 20020168825
    Abstract: A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.
    Type: Application
    Filed: December 28, 2001
    Publication date: November 14, 2002
    Inventors: Byong-man Kim, Soo-doo Chae, Hee-soon Chae, Won-il Ryu
  • Patent number: 6479365
    Abstract: A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: November 12, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jo-won Lee, Chung-woo Kim, Byong-man Kim, Moon-kyung Kim
  • Publication number: 20020088969
    Abstract: A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
    Type: Application
    Filed: March 5, 2002
    Publication date: July 11, 2002
    Inventors: Jo-won Lee, Chung-woo Kim, Byong-man Kim, Moon-Kyung Kim
  • Publication number: 20020088996
    Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.
    Type: Application
    Filed: January 10, 2002
    Publication date: July 11, 2002
    Inventors: In-kyeong Yoo, Byong-man Kim
  • Patent number: 6414333
    Abstract: A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: July 2, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jo-won Lee, Chung-woo Kim, Byong-man Kim, Moon-kyung Kim
  • Patent number: 6388268
    Abstract: A semiconducting yttrium-barium-copper-oxygen(YBCO) device which locally converts a semiconducting YBCO film to a nonconducting YBCO film by a conductive atomic force microscope (AFM), a superconducting YBCO device which locally converts a superconducting YBCO film to nonsuperconducting YBCO by an AFM, and manufacturing methods thereof are provided. According to a method of manufacturing a semiconducting YBCO device or a superconducting YBCO device locally converted by an AFM tip, a voltage is applied to the local region of a semiconducting YBCO channel or a superconducting YBCO channel by an AFM tip. This can produce a nonconducting YBCO region or nonsuperconducting YBCO region to thereby manufacture a tunnel junction easily without any patterning process by microfabrication including photolithography and dry/wet etching.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byong-man Kim, Insang Song
  • Publication number: 20020009632
    Abstract: A rewritable data storage using a carbonaceous material writes or erases information represented by the carbonaceous material by means of a current induced electrochemical reaction on a conductive layer, by controlling a voltage applied across the space between a cantilever tip and the conductive layer. Also, the size of the carbonaceous material representing information is controlled by the level of the applied voltage or the application duration.
    Type: Application
    Filed: May 10, 2001
    Publication date: January 24, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byong-man Kim, Yo-sep Min, Jo-won Lee, Nae-sung Lee
  • Patent number: 6313503
    Abstract: A metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (&Dgr;Vth) due to charging of a single electron when the width of a channel of the memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof, are provided. The MNOS memory uses a threshold voltage variation (&Dgr;Vth) due to charging of a single electron occurring when the width of a channel is set to be smaller than or equal to the Debye screen length (LD) which depends on the impurity concentration of a semiconductor substrate.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: November 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jo-won Lee, Moon-kyung Kim, Byong-man Kim, Seok-yeol Yoon, Hyung-lae Roh
  • Patent number: 6268273
    Abstract: A method of fabricating a single electron tunneling (SET) device, the method including forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate, forming a metal layer having a thickness on the order of nanometers between the source and drain electrodes, and forming quantum dots between the source and drain electrodes due to the movement of metal atoms/ions within the metal layer caused by applying a predetermined voltage to the source and drain electrodes. In the manufacture of an SET device, quantum dots can be formed by a simple method instead of an self assembled monolayer (SAM) method or lithographic methods. Thus, SET devices fabricated in this way have no material dependency, and are also applicable to large scale integration (LSI) structures. Also, since quantum dots are obtained by deposition and electromigration, SET devices having the above-described advantages can be mass-produced.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: July 31, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byong-man Kim, Jo-won Lee, Mi-young Kim, Moon-kyoung Kim