Abstract: A clock buffer circuit that generates a clock signal having a random cycle and duty from an input clock signal and a data output circuit including the same. The clock buffer circuit includes a buffer unit configured to receive an input clock signal and generate an internal clock signal and a first clock signal; a delay controller configured to receive the internal clock signal from the buffer unit and generate a delayed control signal according to a first control signal and a second control signal; and a delay unit configured to generate a second clock signal according to the first clock signal received from the buffer unit and the second clock signal received from the delay controller. The delay unit is configured to generate the second clock signal by randomly delaying transmission of the first clock signal.

Abstract: A voltage detection device and a semiconductor device including the same are provided. The voltage detection device includes: a first clock generator which generates a first clock signal having a period that changes according to an external voltage; a second clock generator which generates a second clock signal having a predetermined period corresponding to a reference voltage; and a detector which detects a change of the external voltage by comparing the first clock signal with the second clock signal.

Abstract: A voltage detection device and a semiconductor device including the same are provided. The voltage detection device includes: a first clock generator which generates a first clock signal having a period that changes according to an external voltage; a second clock generator which generates a second clock signal having a predetermined period corresponding to a reference voltage; and a detector which detects a change of the external voltage by comparing the first clock signal with the second clock signal.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A data receiver that is capable of precisely detecting data at high speed even at a high frequency after receiving differential reference signals and data in synchronization with a clock signal, and a method for receiving data, are provided. The receiver includes an amplifier which compares differential reference signals with input data and outputs first differential reference signals based on the results of the comparison; and a folded differential voltage sensor which amplifies the difference between the first differential signals in synchronization with a clock signal and detects the input data.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A system includes modules, a clock generator that generates a first clock signal that is applied to the modules, and a chipset that controls the modules, the chipset having a clock buffer that generates a second clock signal. The system includes a first clock line that transfer the first clock signal to the clock buffer, the first clock line connected between the clock generator and a first termination circuit. The system includes a second clock line that transfer the second clock signal to the modules, the second clock line electrically isolated from the first clock line, the second clock line connected between the clock buffer and a second termination circuit.

Abstract: Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

Abstract: A circuit comprises a comparing means for comparing an internal voltage to a reference voltage for outputting a first driving signal, an internal voltage driving means for outputting the internal voltage in response to the first driving signal; an internal voltage detecting means for detecting the internal voltage and for generating a second driving signal in response to an active signal, and an overdriving control means for controlling the first driving signal in response to the second driving signal.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: An apparatus and method for measuring the electrical characteristics of a semiconductor device in a packaged state, which includes an electrical characteristic measurer which is connected to an electrical element whose electrical characteristics are to be measured and to one pad of the semiconductor device. The measurer is driven in response to a control signal, and outputs a value indicative of the electrical characteristics of the electrical element to the pad. The measurer includes at least an NMOS threshold voltage measurer, an NMOS saturation current measurer, a PMOS threshold voltage measurer, a PMOS saturation current measurer, and a resistance measurer. An accurate electrical characteristic value can be obtained by measuring the characteristics of the element within a semiconductor device in a finished packaged product. In view of the accurate measurement, degradation of characteristics of the semiconductor device and malfunction thereof can be prevented.

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: A circuit comprises a comparing means for comparing an internal voltage to a reference voltage for outputting a first driving signal, an internal voltage driving means for outputting the internal voltage in response to the first driving signal; an internal voltage detecting means for detecting the internal voltage and for generating a second driving signal in response to an active signal, and an overdriving control means for controlling the first driving signal in response to the second driving signal.

Abstract: An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.

Abstract: Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Abstract: An output driver circuit includes a push-pull driver for driving an output signal of a semiconductor device to one of two voltage levels corresponding to a determined data state. The push-pull driver includes a pull-up driving circuit for driving the output signal toward a first voltage level when the data state is logic “high,” and a pull-down driving circuit for driving the output signal to a second voltage level when the data state is “low.” The strength with which the pull-up driving circuit drives the voltage level of the output signal toward the first output voltage level can be controlled independently of the strength with which the pull-down driving circuit drives the voltage level of the output signal toward the second output voltage level.

Abstract: Described is a receiver circuit reducing kick -back noises, due to coupling capacitance from a pair of differential input transistors when a system clock is rising up to a high level, by connecting drain nodes of the differential input transistors, which respond to a reference voltage and a data signal, respectively, while the system clock is at a low level, to a ground voltage.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.