Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract: An output driver circuit includes a push-pull driver for driving an output signal of a semiconductor device to one of two voltage levels corresponding to a determined data state. The push-pull driver includes a pull-up driving circuit for driving the output signal toward a first voltage level when the data state is logic “high,” and a pull-down driving circuit for driving the output signal to a second voltage level when the data state is “low.” The strength with which the pull-up driving circuit drives the voltage level of the output signal toward the first output voltage level can be controlled independently of the strength with which the pull-down driving circuit drives the voltage level of the output signal toward the second output voltage level.

Abstract: An output driver of a semiconductor integrated circuit having low power consumption and reduced layout area transmits internally generated data of the circuit to pads responsive to clock signals, and is controlled by control signals indicative of changes of process, voltage, and temperature. The output driver includes a data selector, an output driver enabler, a first driver that transmits an output of the output driver enabler to the pads, and a second driver that includes a data delay having a plurality of inverters connected in series to an output of the output driver enabler and being activated responsive to the control signals. The second driver transmits an output of the data delay to the pads. The output driver reduces a load on the clock signal line, so that power consumption and a layout area can be reduced.

Abstract: An information processing system preferably includes a divided clock line structure, in which a first clock line transferring a CTM clock signal is electrically isolated from a second clock line transferring a CFM clock signal. Using the CTM clock signal, a chipset generates anew the CFM clock signal transferred through the second clock line to prevent clock signal degradation.

Abstract: Described is a receiver circuit reducing kick-back noises, due to coupling capacitance from a pair of differential input transistors when a system clock is rising up to a high level, by connecting drain nodes of the differential input transistors, which respond to a reference voltage and a data signal, respectively, while the system clock is at a low level, to a ground voltage.

Abstract: A data receiver that is capable of precisely detecting data at high speed even at a high frequency after receiving differential reference signals and data in synchronization with a clock signal, and a method for receiving data, are provided. The receiver includes an amplifier which compares differential reference signals with input data and outputs first differential reference signals based on the results of the comparison; and a folded differential voltage sensor which amplifies the difference between the first differential signals in synchronization with a clock signal and detects the input data.

Abstract: An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.

Abstract: An apparatus and method for measuring the electrical characteristics of a semiconductor device in a packaged state, which includes an electrical characteristic measurer which is connected to an electrical element whose electrical characteristics are to be measured and to one pad of the semiconductor device. The measurer is driven in response to a control signal, and outputs a value indicative of the electrical characteristics of the electrical element to the pad. The measurer includes at least an NMOS threshold voltage measurer, an NMOS saturation current measurer, a PMOS threshold voltage measurer, a PMOS saturation current measurer, and a resistance measurer. An accurate electrical characteristic value can be obtained by measuring the characteristics of the element within a semiconductor device in a finished packaged product. In view of the accurate measurement, degradation of characteristics of the semiconductor device and malfunction thereof can be prevented.

Abstract: An output driver of a semiconductor integrated circuit having low power consumption and reduced layout area transmits internally generated data of the circuit to pads responsive to clock signals, and is controlled by control signals indicative of changes of process, voltage, and temperature. The output driver includes a data selector, an output driver enabler, a first driver that transmits an output of the output driver enabler to the pads, and a second driver that includes a data delay having a plurality of inverters connected in series to an output of the output driver enabler and being activated responsive to the control signals. The second driver transmits an output of the data delay to the pads. The output driver reduces a load on the clock signal line, so that power consumption and a layout area can be reduced.

Abstract: An integrated circuit memory device is provided which includes input buffers placed adjacent an associated input shift block rather than displaced with intervening regions, such as a pad block, between the buffer and the shift block. As a result, a single input clock line may be provided which can support both the input buffers and the shift block. The single line may also provide less loading allowing a lower power driver in the memory device's clock circuit. In addition, the input clock line may avoid routing through the pad block which in turn may reduce noise on the input clock line from signals in the pad block. The output buffers and associated shift block may also be located adjacent each other on the on the integrated circuit memory device to allow similar benefits on the output clock side of the memory device. Accordingly, memory devices are provided which may consume less power and be reduced in size. The integrated circuit memory device may be a Rambus DRAM.