Patents by Inventor Byoung-Ho Kwon
Byoung-Ho Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951130Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.Type: GrantFiled: March 1, 2021Date of Patent: April 9, 2024Assignee: Eutilex Co., Ltd.Inventors: Byoung S. Kwon, Young Ho Kim, Kwang Hee Kim, Ji Won Chung, Young Gyoon Chang, Bo Rim Yi, Jung Yun Lee, Seung Hyun Lee, Sun Woo Im, Jin Kyung Choi, Hyun Tae Son, Eun Hye Yoo
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Publication number: 20230219191Abstract: The present disclosure provides a polishing pad and a method of manufacturing a semiconductor device using the same. The method includes disposing a target layer on a semiconductor substrate and performing a chemical mechanical polishing process on the target layer using a polishing pad including a plurality of polishing protrusions facing the target layer. Each of the polishing protrusions includes a protruding portion and a surface layer at least partially covering the protruding portion, wherein the protruding portion is more elastic than the surface layer, and wherein the surface layer is harder than the protruding portion.Type: ApplicationFiled: June 7, 2022Publication date: July 13, 2023Applicant: Korea Advanced Institute of Science and TechnologyInventors: Sanha KIM, Ji Su KIM, Yeong Bong PARK, Hyun Jun RYU, Myung-Ki HONG, Byoung Ho KWON, Dong Geun KIM, Ji-Hun JEONG, Sukkyung KANG
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Patent number: 11637019Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.Type: GrantFiled: August 3, 2021Date of Patent: April 25, 2023Inventors: Chang Sun Hwang, Han Sol Seok, Hyun Ku Kang, Byoung Ho Kwon, Chung Ki Min
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Publication number: 20220118582Abstract: A chemical mechanical polishing method is provided. A chemical mechanical polishing method comprising providing a polishing pad, supplying a first purging compound having a first temperature onto the polishing pad, supplying a first slurry having a third temperature onto the polishing pad supplied with the first purging compound, supplying a second purging compound having a second temperature lower than the first temperature onto the polishing pad, and supplying a second slurry having a fourth temperature lower than the third temperature onto the polishing pad supplied with the second purging compound.Type: ApplicationFiled: August 12, 2021Publication date: April 21, 2022Inventors: Myung-Ki HONG, Youg Hee LEE, Byoung Ho Kwon, Kun Tack LEE
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Publication number: 20210366720Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: CHANG SUN HWANG, HAN SOL SEOK, HYUN KU KANG, BYOUNG HO KWON, CHUNG KI MIN
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Patent number: 11087990Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.Type: GrantFiled: June 6, 2019Date of Patent: August 10, 2021Inventors: Chang Sun Hwang, Han Sol Seok, Hyun Ku Kang, Byoung Ho Kwon, Chung Ki Min
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Patent number: 10964303Abstract: A vehicular apparatus for active noise control may include: a sensing unit configured to sense information characterizing at least one of an environment inside of a vehicle and an environment outside of the vehicle; and a controller configured extract road roughness information characterizing road roughness from the sensed information, to calculate a convergence coefficient based on the road roughness information, to generate a control signal by applying the convergence coefficient to a control filter coefficient, and to perform active noise control using the control signal.Type: GrantFiled: July 15, 2019Date of Patent: March 30, 2021Assignees: Hyundai Motor Company, Kia Motors CorporationInventor: Byoung Ho Kwon
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Publication number: 20200327876Abstract: A vehicular apparatus for active noise control may include: a sensing unit configured to sense information characterizing at least one of an environment inside of a vehicle and an environment outside of the vehicle; and a controller configured extract road roughness information characterizing road roughness from the sensed information, to calculate a convergence coefficient based on the road roughness information, to generate a control signal by applying the convergence coefficient to a control filter coefficient, and to perform active noise control using the control signal.Type: ApplicationFiled: July 15, 2019Publication date: October 15, 2020Inventor: Byoung Ho Kwon
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Patent number: 10741409Abstract: A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.Type: GrantFiled: October 2, 2017Date of Patent: August 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo Jung Kim, Ye Hwan Kim, Ki Hoon Jang, Byoung Ho Kwon, Bo Un Yoon
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Publication number: 20200090943Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.Type: ApplicationFiled: June 6, 2019Publication date: March 19, 2020Inventors: CHANG SUN HWANG, HAN SOL SEOK, HYUN KU KANG, BYOUNG HO KWON, CHUNG KI MIN
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Patent number: 10403640Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.Type: GrantFiled: March 22, 2018Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Chang Sun Hwang, Ki Chul Park, Young Beom Pyon, Byoung Ho Kwon, Bo Un Yoon
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Publication number: 20190074289Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.Type: ApplicationFiled: March 22, 2018Publication date: March 7, 2019Inventors: Chang Sun Hwang, Ki Chul Park, Young Beom Pyon, Byoung Ho Kwon, Bo Un Yoon
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Patent number: 10109529Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.Type: GrantFiled: June 17, 2016Date of Patent: October 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Koh, Byoung-ho Kwon, Yang-hee Lee, Young-kuk Kim, In-seak Hwang, Bo-un Yoon
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Publication number: 20180130672Abstract: A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.Type: ApplicationFiled: October 2, 2017Publication date: May 10, 2018Applicant: Samsung Electronics Co., Ltd .Inventors: Hyo Jung Kim, Ye Hwan Kim, Ki Hoon Jang, Byoung Ho Kwon, Bo Un Yoon
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Patent number: 9960169Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.Type: GrantFiled: August 22, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Seok Lee, Byoung-Ho Kwon, Sang-Kyun Kim, Yun-Jeong Kim, Seung-Ho Park, Hao Cui, In-Seak Hwang
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Patent number: 9831186Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.Type: GrantFiled: June 11, 2015Date of Patent: November 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-hyun Park, Byoung-ho Kwon, Dong-chan Kim, Choong-seob Shin, Jong-su Kim, Bo-un Yoon
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Patent number: 9659940Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.Type: GrantFiled: July 6, 2016Date of Patent: May 23, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-sung Park, In-seak Hwang, Bo-un Yoon, Byoung-ho Kwon, Jong-hyuk Park, Jae-hee Kim, Myung-jae Jang
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Patent number: 9627542Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: GrantFiled: May 2, 2016Date of Patent: April 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
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Publication number: 20170098653Abstract: Methods of manufacturing a semiconductor device are provided. Methods may include forming first to third regions having densities different from one another on a substrate, covering the first to third regions to form an upper interlayer insulating film including a low step portion and a high step portion higher than the low step portion, forming an organic film on the upper interlayer insulating film, removing a part of the organic film to expose an upper surface of the high step portion, removing the high step portion so that an upper surface of the high step portion is disposed on at least the same line as the organic film disposed on the upper surface of the lower step portion, removing the remaining part of the organic film to expose the upper surface of the upper interlayer insulating film and flattening the upper surface of the upper interlayer insulating film.Type: ApplicationFiled: June 15, 2016Publication date: April 6, 2017Inventors: Young-Ho Koh, Hye-Sung Park, Byoung-Ho Kwon, Jong-Hyuk Park, Bo-Un Yoon, ln-Seak Hwang
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Publication number: 20170084710Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.Type: ApplicationFiled: June 17, 2016Publication date: March 23, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Young-ho Koh, Byoung-ho Kwon, Yang-hee Lee, Young-kuk Kim, In-seak Hwang, Bo-un Yoon