Patents by Inventor Byoung-Ho Kwon
Byoung-Ho Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170077103Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.Type: ApplicationFiled: July 6, 2016Publication date: March 16, 2017Inventors: Hye-sung Park, ln-seak Hwang, Bo-un Yoon, Byoung-ho Kwon, Jong-hyuk Park, Jae-hee Kim, Myung-jae Jang
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Publication number: 20170062437Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.Type: ApplicationFiled: August 22, 2016Publication date: March 2, 2017Inventors: Jun-Seok Lee, Byoung-Ho Kwon, Sang-Kyun Kim, Yun-Jeong Kim, Seung-Ho Park, Hao Cui, ln-Seak Hwang
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Publication number: 20160247925Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
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Publication number: 20160079260Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.Type: ApplicationFiled: June 3, 2015Publication date: March 17, 2016Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
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Publication number: 20160064380Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: ApplicationFiled: November 5, 2015Publication date: March 3, 2016Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
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Patent number: 9269720Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.Type: GrantFiled: June 3, 2015Date of Patent: February 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-woo Bae, Byoung-ho Kwon, Jong-hyuk Park, Hye-sung Park, Jun-seok Lee, Ki-vin Im, Hee-sook Cheon, In-seak Hwang
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Publication number: 20160027739Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.Type: ApplicationFiled: June 11, 2015Publication date: January 28, 2016Inventors: Ki-hyun Park, Byoung-ho KWON, Dong-chan KIM, Choong-seob SHIN, Jong-su KIM, Bo-un YOON
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Patent number: 9190407Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: GrantFiled: December 12, 2014Date of Patent: November 17, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
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Patent number: 9035396Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: GrantFiled: September 22, 2011Date of Patent: May 19, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
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Publication number: 20150097251Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Inventors: Byoung-Ho KWON, Cheol KIM, Ho-Young KIM, Se-Jung PARK, Myeong-Cheol KIM, Bo-Kyeong KANG, Bo-Un YOON, Jae-Kwang CHOI, Si-Young CHOI, Suk-Hoon JEONG, Geum-Jung SEONG, Hee-Don JEONG, Yong-Joon CHOI, Ji-Eun HAN
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Patent number: 8916460Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.Type: GrantFiled: May 5, 2014Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
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Patent number: 8736058Abstract: A conductive structure includes a contact plug extending through an insulating layer on a substrate, and first and second conductive lines extending alongside one another on the insulating layer. The first conductive line extends on the contact plug. A connecting line on the insulating layer extends between and electrically connects the first and second conductive lines. Related integrated circuit devices and fabrication methods are also discussed.Type: GrantFiled: October 22, 2010Date of Patent: May 27, 2014Assignee: Samsung Electronics CorporationInventors: Byoung-Ho Kwon, Bo-Un Yoon
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Patent number: 8597081Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.Type: GrantFiled: September 23, 2011Date of Patent: December 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Kwang Choi, Hong-Jin Kim, Keon-Sik Seo, Sol Han, Kun-Tack Lee, Byoung-Ho Kwon
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Patent number: 8398874Abstract: A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.Type: GrantFiled: November 24, 2010Date of Patent: March 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-Ho Kwon, Bo-Un Yoon, Min-Sang Kim
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Patent number: 8241988Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.Type: GrantFiled: August 8, 2011Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jae-dong Lee, Sang-jin Kim
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Publication number: 20120083189Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.Type: ApplicationFiled: September 23, 2011Publication date: April 5, 2012Inventors: Jae-Kwang Choi, Hong-Jin Kim, Keon-Sik Seo, Sol Han, Kun-Tack Lee, Byoung-Ho Kwon
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Publication number: 20120028435Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: ApplicationFiled: September 22, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
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Publication number: 20110294285Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jae-dong Lee, Sang-jin Kim
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Patent number: 8053845Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.Type: GrantFiled: November 7, 2008Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
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Patent number: 8030150Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.Type: GrantFiled: March 4, 2009Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jun-yong Kim