Abstract: A multilater ceramic capacitor includes: a ceramic body in which a plurality of dielectric layers are laminated; and an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layer interposed therebetween, and forming capacitance. An upper cover layer is formed on an upper portion of the active layer; a lower cover layer is formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer. First and second external electrodes cover both end surfaces of the ceramic body. Specific sizing of ceramic body and electrodes is defined.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, disposed vertically on upper and lower surfaces of the ceramic body and forming capacitance; an upper cover layer formed upwardly of the active layer; a lower cover layer formed downwardly of the active layer and having a thickness greater than that of the upper cover layer; and first and second external electrodes covering both end surfaces of the ceramic body, wherein the active layer includes a first block in which a first region I and a second region II formed, and a second block in which a third region III, and a fourth region IV formed.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer formed having a thickness greater than that of the upper cover layer; and first and second external electrodes, wherein when an average of a length of an upper portion, a length of a middle portion, and a length of a lower portion of the ceramic body is I, and an average of values obtained by adding a length of an upper portion, a length of a middle portion, and a length of a lower portion of the first external electrode and a length of an upper portion, a length of a middle portion, and a length of a lower portion of the second external electrode is BW, BW/I satisfies a range of 0.105?BW/I?1.049.

Abstract: There is provided an embedded multilayer ceramic electronic component, including: a ceramic body including dielectric layers; first and second internal electrodes facing each other with the dielectric layers interposed therebetween; a first external electrode and a second external electrode formed on external surfaces of the ceramic body, the first external electrode being electrically connected to the first internal electrodes and the second external electrode being electrically connected to the second internal electrodes; and a plating layer formed on the first external electrode and the second external electrode, wherein a surface roughness of the ceramic body is 500 nm or greater and not greater than a thickness of a ceramic cover sheet and a surface roughness of the plating layer is 300 nm or greater and not greater than a thickness of the plating layer.

Abstract: There is provided a multilayered ceramic capacitor including: a ceramic body in which a plurality of dielectric layers are stacked; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance; an upper cover layer formed above the active layer, a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes formed to cover both end surfaces of the ceramic body, wherein a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9.

Abstract: The present invention relates to an electronic component embedded printed circuit board and a method for manufacturing the same. An electronic component embedded printed circuit board of the present invention includes a core having a cavity; an electronic component inserted in the cavity and having a bonding coating layer on an outer peripheral surface; insulating layers laminated on and under the core and in contact with the bonding coating layer; and circuit patterns provided on the insulating layers.

Abstract: A multilayered ceramic capacitor includes a ceramic body in which a plurality of dielectric layers having an average thickness of 0.2 to 2.0 ?m are stacked; an active layer including a plurality of first and second internal electrodes alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance; an upper cover layer formed above the active layer; a lower cover layer formed below the active layer and thicker than the upper cover layer; and first and second external electrodes covering both end surfaces of the ceramic body, wherein the dielectric layer is configured of dielectric grains, and when an average thickness of the dielectric layer is defined as td, an average thickness of the first and second internal electrodes is defined as te, and an average grain size of the dielectric grains is defined as Da, Da?td/3 and 0.2 ?m<te<(td)1/2 are satisfied.

Abstract: There is provided a multilayered ceramic capacitor, including: a ceramic body having a plurality of dielectric layers laminated therein; an active layer including a plurality of internal electrodes having the respective dielectric layers interposed therebetween; an upper cover layer; a lower cover layer; external electrodes; and a plurality of dummy electrodes, wherein, when A is defined as ½ of an overall thickness of the ceramic body, B is defined as the thickness of the lower cover layer, C is defined as ½ of an overall thickness of the active layer, and D is defined as the thickness of the upper cover layer, a ratio of deviation between a center portion of the active layer and a center portion of the ceramic body, (B+C)/A, satisfies 1.063?(B+C)/A?1.745.

Abstract: There is provided a multilayered ceramic capacitor, including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer formed below the active layer, the lower cover layer being thicker than the upper cover layer; first and second external electrodes; at least one pair of first and second internal electrodes repeatedly formed inside the lower cover layer, wherein, when A is defined as ½ of an overall thickness of the ceramic body, B is defined as a thickness of the lower cover layer, C is defined as ½ of an overall thickness of the active layer, and D is defined as a thickness of the upper cover layer, a ratio of deviation between a center of the active layer and a center of the ceramic body, (B+C)/A, satisfies 1.063?(B+C)/A?1.745.

Abstract: The present invention relates to a multilayer ceramic capacitor and a printed circuit board including the same that can minimize thickness deviations of an external electrode and a multilayer ceramic. A multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer ceramic and external electrodes formed on both sides of the multilayer ceramic, wherein |Tmax?Tmin| may be less than 10 ?m, and |CTmax?CTmin| may be less than 20 ?m. (Here, Tmax is a maximum thickness of the external electrodes in a via processing area, Tmin is a minimum thickness of the external electrodes in the via processing area, CTmax is a maximum thickness of the multilayer ceramic capacitor in the via processing area, and CTmin is a minimum thickness of the multilayer ceramic capacitor in the via processing area.

Abstract: There is provided a multilayered chip electronic component including: a ceramic body including internal electrodes and dielectric layers; external electrodes covering both end surfaces of the ceramic body in a length direction; first plating layers forming the external electrodes and formed on outer surfaces of the ceramic body; non-conductive layers formed on outer side surfaces of the first plating layers; and second plating layers formed on regions of the first plating layers except for the non-conductive layers.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract: There are provided a laminated ceramic electronic component and a method of fabricating the same. The laminated ceramic electronic component include a ceramic body including a dielectric layer; and first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween within the ceramic body, wherein the ceramic body includes an active layer that is a capacitance forming part and a cover layer that is a non-capacitance forming part formed on at least one of a top surface and a bottom surface of the active layer, and when a thickness of the ceramic body is t and a thickness of the cover layer is T, T?t×0.05 is satisfied and when an average particle diameter of a dielectric grain in the active layer is Da and an average particle diameter of a dielectric grain in the cover layer is Dc, 0.7?Dc/Da?1.5 is satisfied.

Abstract: A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body formed by laminating dielectric layers having an average thickness of 0.7p or less; external electrodes formed on external surfaces of the ceramic body; and internal electrodes respectively disposed on the dielectric layer so as to have a gap formed therebetween, wherein, when a narrowest gap between the internal electrode edges adjacent to one another is denoted by Gmin, 10 ?m?Gmin?60 ?m is satisfied.

Abstract: There are provided an electronic component and a fabrication method thereof. The electronic component includes: a ceramic main body including end surfaces in a length direction, side surfaces in a width direction and top and bottom surfaces in a thickness direction; first and second external electrodes formed on the end surfaces, respectively; third and fourth external electrodes formed on the side surfaces, respectively; first internal electrodes formed within the ceramic main body and connected to first and second external electrodes; and second internal electrodes alternately arranged with the first internal electrodes, while having a ceramic layer interposed therebetween, and connected to the third and fourth external electrodes, wherein thickness t1 and t2 of the first and second internal electrodes is 0.9 ?m or less, while a roughness R1 of the first internal electrode is lower than a roughness R2 of the second internal electrode.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body having external electrodes; and internal electrodes disposed between ceramic layers within the ceramic body, the ceramic body having a width smaller than a length thereof and the number of laminated internal electrodes being 250 or more, wherein when the thickness of the ceramic layer is denoted by Td and the thickness of the internal electrode is denoted by Te, 0.5?Te/Td?2.0, and when the thickness of a central portion of the ceramic body is denoted by Tm and the thickness of each of side portions of the ceramic body is denoted by Ta, 0.9?Ta/Tm?0.97, and thus, a multilayer ceramic electronic component having low equivalent series inductance (ESL) may be obtained.

Abstract: A multilayer ceramic electronic component having high reliability by reducing equivalent series resistance (ESR) dispersion is provided. Connectivity between internal electrodes and external electrodes is secured by introducing dummy electrodes connected to first and second terminal electrodes, to third and fourth internal electrode layers. ESR dispersion of the multilayer ceramic electronic component is reduced to obtain high reliability.

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.