Abstract: An active roll control apparatus is provided. The apparatus includes a first actuator that is disposed adjacent to front wheels or rear wheels and is configured to adjust roll stiffness. A controller operates the first actuator in a reverse phase control manner in a roll angle increasing direction when a vehicle is in a low-friction turning driving state.

Abstract: A semiconductor device includes a first processor configured to process a first code based on a first clock signal; and a second processor, controlled by the first processor, electrically coupled to a memory, and configured to process a second code based on the first clock signal and a second clock signal, wherein the second clock signal has a faster cycle than the first clock signal.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: The present invention relates to a method for providing payment information, for example, to a device for providing payment information by using a sensor, and a method therefor. To this end, an electronic device, of the present invention, comprising a first communication circuit, a second communication circuit, a sensor, and a processor, can comprise the operations of: receiving a user input by using the sensor; performing authentication on the user input; receiving payment information from an external electronic device by using the first communication circuit when the authentication has been successful; and outputting the payment information through the second communication circuit when a complete event for the user input has been received from the sensor by using the processor.

Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.

Abstract: A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.

Abstract: A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.

Abstract: A method for use in an electronic device includes: receiving, from a server, beacon information including a first function information. The first function information is associated with a first function, and the first function is executed in response to detecting that a beacon signal that is received from a beacon transmitter matches beacon information.

Abstract: A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.

Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.

Abstract: Provided is a binding device and method of operation of the binding device, with the binding device including a strap including a body, a first area formed inside the body, with a smart key related control circuit disposed in the first area, and a second area formed on one side of the body, with a battery for supplying electric power for operating the smart key related control circuit seated on the second area such that at least a portion of the battery is exposed, and a cover formed to cover the second area.

Abstract: A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.

Abstract: Disclosed is a method of driving a semiconductor memory device, which programs first page data and second page data in a selected page of a memory cell array, the method including: transmitting a first data buffer control signal to a data buffer so that a data buffer receives the first page data; transmitting a second data buffer control signal to the data buffer so that the data buffer receives the second page data; determining a program option of the first page data; and programming the first page data and the second page data in the selected page, in which the data buffer receives at least some elements of the second page data while the determining of the program option of the first page data is performed.

Abstract: A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.

Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.

Abstract: There are provided a semiconductor memory device and an operating method thereof. The method of operating a semiconductor memory device may include receiving an erase and write (E/W) cycle mode select command and an operation command. The method may include selecting one E/W cycle mode information among a plurality of E/W cycle mode information stored according to the E/W cycle mode select command and storing the selected one E/W cycle mode information. The method may include performing a general operation of a memory cell array according to the one E/W cycle mode information stored and the operation command.

Abstract: A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation.

Abstract: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Abstract: The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an LSB program state or an MSB program state.