Abstract: A method of manufacturing a NAND flash memory device, wherein isolation layers are formed in a semiconductor substrate, and an upper side of each of the isolation layers is made to have a negative profile. A polysilicon layer is formed on the entire surface. At this time, a seam is formed within the polysilicon layer due to the negative profile. A post annealing process is performed in order to make the seam to a void. Accordingly, an electrical interference phenomenon between cells can be reduced and a threshold voltage (Vt) shift value can be lowered.

Abstract: In a method of manufacturing an SONOS type flash memory device, a first oxide layer and a buffer poly layer are formed over a surface of a semiconductor except for a memory cell region of a cell region. A second oxide layer, a nitride layer and a third oxide layer are formed. The poly buffer layer is exposed by etching specific regions in a peri region and in a DSL/SSL region of the cell region. A conductive layer is formed to electrically connect to the poly buffer layer. The third oxide layer, the nitride layer and the second nitride layer are selectively etched to form a gate of the memory cell region of the cell region. The buffer poly layer is selectively etched to form a gate in the DSL/SSL region of the cell region and a gate in the peri region.

Abstract: In a method of manufacturing an SONOS type flash memory device, a first oxide layer and a buffer poly layer are formed over a surface of a semiconductor except for a memory cell region of a cell region. A second oxide layer, a nitride layer and a third oxide layer are formed. The poly buffer layer is exposed by etching specific regions in a peri region and in a DSL/SSL region of the cell region. A conductive layer is formed to electrically connect to the poly buffer layer. The third oxide layer, the nitride layer and the second nitride layer are selectively etched to form a gate of the memory cell region of the cell region. The buffer poly layer is selectively etched to form a gate in the DSL/SSL region of the cell region and a gate in the peri region.

Abstract: A method of manufacturing a flash memory device.

Abstract: A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.

Abstract: A method of manufacturing a NAND flash memory device, wherein isolation layers are formed in a semiconductor substrate, and an upper side of each of the isolation layers is made to have a negative profile. A polysilicon layer is formed on the entire surface. At this time, a seam is formed within the polysilicon layer due to the negative profile. A post annealing process is performed in order to make the seam to a void. Accordingly, an electrical interference phenomenon between cells can be reduced and a threshold voltage (Vt) shift value can be lowered.

Abstract: A method of manufacturing a non-volatile memory device includes forming first and second isolation structures in a substrate. A tunnel dielectric layer, a first conductive layer, a first insulating layer, and a second insulating layer are provided between the first and second isolation structures. The first and second insulating layers are removed to expose the first conductive layer. First and second vertical extensions are formed on the first conductive layer to form a U-shape structure. Upper portions of the first and second isolation structures are removed to define second gate trenches, so that each vertical extension has first and second sides exposed. A dielectric layer and a second conductive layer are formed to form a gate structure comprising the first conductive layer, the dielectric layer, and the second conductive layer.

Abstract: The present invention relates to a method of fabricating a flash memory device. According to the present invention, an oxide film is deposited and etched to form trenches, the trenches are filled with a metal film, and the metal film undergoes CMP to form bit lines. In this case, an etch stop layer of the trench etch process, a CMP stop layer of a CMP process and a wet barrier on the sides of the trenches are formed using a thermally treated SiON film having an etch rate lower than that of a wet chemical. As such, since a thickness and width of bit lines can be made uniform, bit line resistance and capacitance can be maintained constantly.

Abstract: The present invention discloses a method for manufacturing a flash memory device including the steps of: sequentially forming a first polysilicon film for a floating gate electrode, a first oxide film, a polysilicon film for a hard mask and a second oxide film on a semiconductor substrate; etching and patterning the second oxide film and the polysilicon film for the hard mask, by forming photoresist patterns on a predetermined region of the second oxide film, and removing the photoresist patterns; forming spacers on the sidewalls of the polysilicon film for the hard mask, by forming and etching a polysilicon film for forming spacers on the whole surface of the resulting structure; removing the exposed first oxide film and a predetermined thickness of second oxide film formed on the patterned polysilicon film for the hard mask; forming floating gate electrode patterns by performing first and second etching processes by using the patterned polysilicon film for the hard mask and the spacers as an etch mask; perf

Abstract: The present invention relates to a method of manufacturing a flash memory device. In a flash memory device formed by applying a self-align shallow trench isolation (SA-STI) scheme, a polishing process and a process for removing a nitride film are performed after oxide materials are buried in isolation trenches. Then, oxide films with an excellent planarization are formed, a first etching process is performed to selectively remove the oxide films in a low voltage transistor/cell area to a certain thickness, a second etching process is performed to remove the oxide films in a high voltage transistor area and the low voltage transistor/cell area until a poly-silicon layer for a floating gate is exposed. Therefore, protruding portions of element isolation films in the high voltage transistor area and the low voltage transistor/cell area are etched away to a certain thickness during the first and second etching processes so that a difference in EFH's between these areas can be reduced.

Abstract: The present invention relates to a method of manufacturing a flash memory device. In a flash memory device formed by applying a self-align shallow trench isolation (SA-STI) scheme, a polishing process and a process for removing a nitride film are performed after oxide materials are buried in isolation trenches. Then, oxide films with an excellent planarization are formed, a first etching process is performed to selectively remove the oxide films in a low voltage transistor/cell area to a certain thickness, a second etching process is performed to remove the oxide films in a high voltage transistor area and the low voltage transistor/cell area until a poly-silicon layer for a floating gate is exposed. Therefore, protruding portions of element isolation films in the high voltage transistor area and the low voltage transistor/cell area are etched away to a certain thickness during the first and second etching processes so that a difference in EFH's between these areas can be reduced.

Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1−x)(TiyN1−y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has the advantage of providing an effective low cost in manufacturing process for single crystals by using a conventional heat-treatment process without the need of special equipment.

Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1-x)(TiyN1-y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has the advantage of providing an effective low cost in manufacturing process for single crystals by using a conventional heat-treatment process without the need of special equipment.

Abstract: The invention relates to a method for growing single crystals of barium titanate [BaTiO3] and barium titanate solid solutions [(BaxM1-x)(TiyN1-y)O3]. This invention is directed to a method for growing single crystals of barium titanate or barium titanate solid solutions showing the primary and secondary abnormal grain growths with increasing temperature higher than the liquid formation temperature, characterized by comprising the step for a few secondary abnormal grains to continue to grow at a temperature slightly below the critical temperature where the secondary abnormal grain growth starts to occur. The method for growing single crystals of barium titanate or barium titanate solid solutions according to this invention has an advantage to provide an effective low cost in manufacturing process for single crystals by using usual heat-treatment process without special equipments.

Abstract: A distributor with controlled switching elements (CSE) which simplifies hardware construction by distributing the function of a running adder into a reverse banyan network. The distributor comprises a CSE-based network using switching stages, each switching stage having control switching elements. A control signal input stage switches two packet input signal switching channels, each stage receiving each control signal from an output stage having switching elements. An active packet counter counts and generates an output signal which represents the number of active packets inputted to the CSE network. A tail-of-queue register is used for storing output vectors.