Patents by Inventor Byoung Hoon Lee
Byoung Hoon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967630Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: GrantFiled: February 11, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
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Patent number: 11966768Abstract: Disclosed herein are an apparatus and method for a multi-cloud service platform. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may receive a service request from a user client device, generate a multi-cloud infrastructure service using multiple clouds in response to the service request, make the multiple clouds interoperate with mufti-cloud infrastructure in order to provide the multi-cloud infrastructure service, and generate a multi-cloud application runtime environment corresponding to the multi-cloud infrastructure service.Type: GrantFiled: February 3, 2021Date of Patent: April 23, 2024Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seok-Ho Son, Dong-Jae Kang, Byoung-Seob Kim, Seung-Jo Bae, Ji-Hoon Seo, Byeong-Thaek Oh, Kure-Chel Lee, Young-Woo Jung
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Patent number: 11949012Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: December 8, 2020Date of Patent: April 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Publication number: 20240107818Abstract: A display module may include a display panel that includes a base layer, a circuit insulating layer, a first electrode, and an emission layer. The circuit insulating layer may include a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness. The first electrode may include a first electrode portion disposed on the first portion and a second electrode portion extending from the first electrode portion and disposed on the second portion. The emission layer may include a first light-emitting portion disposed on the first electrode portion and a second light-emitting portion extending from the first light-emitting portion and disposed on the second electrode portion.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Seung-Hoon LEE, SANGMIN KIM, Byoung-Hun SUNG
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Patent number: 11914773Abstract: Provided is a brain-machine interface based intention determination device using a virtual environment, including: an input unit that receives a control mode; a training output unit that outputs training information; a collection unit that collects a brain signal; a first preprocessing unit that extracts time-frequency information; a second preprocessing unit that generates physical information; a learning unit that learns control information according to a pattern of physical information; a determination unit that determines control information; and a command output unit that outputs a control command matching the control information.Type: GrantFiled: January 20, 2021Date of Patent: February 27, 2024Assignee: Korea University Research and Business FoundationInventors: Seong-Whan Lee, Byoung-Hee Kwon, Ji-Hoon Jeong, Kyung-Hwan Shim, Byeong-Hoo Lee
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Publication number: 20230378263Abstract: A semiconductor device includes an active pattern; gate spacers on the active pattern defining a gate trench; a gate insulating layer along a sidewall and a bottom surface of the gate trench; a first conductive layer on the gate insulating layer; a second conductive layer on the first conductive layer in the gate trench; a third conductive layer on the second conductive layer in the gate trench and including a first portion between parts of the second conductive layer, and a second portion on the first portion and in contact with an upper surface of the second conductive layer; and a capping pattern on the second and third conductive layers and including a portion between the gate insulating layer and the second portion, and in contact with a sidewall of the second portion, wherein a width of the second portion is greater than a width of the first portion.Type: ApplicationFiled: December 21, 2022Publication date: November 23, 2023Inventors: Jin Kyu JANG, Byoung Hoon LEE, Chan Hyeong LEE, Nam Gyu CHO
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Patent number: 11588039Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: GrantFiled: November 25, 2019Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong Lee, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Publication number: 20220267912Abstract: A catalyst for producing hydrogen peroxide and a preparation method therefor are provided. The catalyst for producing hydrogen peroxide according to the embodiments of the present invention comprises a carbon-based support and a catalyst moiety that is bonded to the carbon-based support and comprises an M1-N bonding structure (M1 represents a transition metal atom). The method for preparing a catalyst for producing hydrogen peroxide according to the embodiments of the present invention comprises comprises preparing a carbon-based support, providing a transition metal atom (M1) to the carbon-based support, and doping nitrogen into the carbon-based support.Type: ApplicationFiled: July 21, 2020Publication date: August 25, 2022Inventors: Taeghwan HYEON, Yung-Eun SUNG, Heejong SHIN, Byoung-Hoon LEE, Euiyeon JUNG
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Publication number: 20220254884Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.Type: ApplicationFiled: October 18, 2021Publication date: August 11, 2022Inventors: Jae-Jung KIM, Sang Yong KIM, Byoung Hoon LEE, Chan Hyeong LEE
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Publication number: 20220165861Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Byoung Hoon LEE, Wan Don KIM, Jong Ho PARK, Sang Jin HYUN
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Patent number: 11282939Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.Type: GrantFiled: February 7, 2019Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Hoon Lee, Wan Don Kim, Jong Ho Park, Sang Jin Hyun
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Patent number: 11177364Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: July 24, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Publication number: 20210119058Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: ApplicationFiled: December 8, 2020Publication date: April 22, 2021Inventors: Jong Ho PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
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Patent number: 10879392Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: GrantFiled: June 25, 2019Date of Patent: December 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho Park, Wan Don Kim, Weon Hong Kim, Hyeon Jun Baek, Byoung Hoon Lee, Jeong Hyuk Yim, Sang Jin Hyun
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Publication number: 20200365706Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: ApplicationFiled: July 24, 2020Publication date: November 19, 2020Inventors: Byoung-Hoon Lee, HOON-JOO NA, SUNG-IN SUH, MIN-WOO SONG, CHAN-HYEONG LEE, HU-YONG LEE, SANG-JIN HYUN
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Patent number: 10770560Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.Type: GrantFiled: December 10, 2018Date of Patent: September 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Hyuk Yim, Kug Hwan Kim, Wan Don Kim, Jung Min Park, Jong Ho Park, Byoung Hoon Lee, Yong Ho Ha, Sang Jin Hyun, Hye Ri Hong
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Patent number: 10756195Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.Type: GrantFiled: November 2, 2018Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hoon Lee, Hoon-Joo Na, Sung-In Suh, Min-Woo Song, Chan-Hyeong Lee, Hu-Yong Lee, Sang-Jin Hyun
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Publication number: 20200098882Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong LEE, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun
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Publication number: 20200013897Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack. includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.Type: ApplicationFiled: June 25, 2019Publication date: January 9, 2020Inventors: JONG HO PARK, Wan Don KIM, Weon Hong KIM, Hyeon Jun BAEK, Byoung Hoon LEE, Jeong Hyuk YIM, Sang Jin HYUN
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Patent number: 10529816Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.Type: GrantFiled: March 8, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hyeong Lee, Hoon-joo Na, Sung-in Suh, Min-woo Song, Byoung-hoon Lee, Hu-yong Lee, Sang-jin Hyun