Patents by Inventor Byoung Wook Jang
Byoung Wook Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11469133Abstract: A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.Type: GrantFiled: March 2, 2020Date of Patent: October 11, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Geun Ahn, Min Keun Kwak, Ji Won Shin, Sang Hoon Lee, Byoung Wook Jang
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Patent number: 11133296Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.Type: GrantFiled: November 27, 2019Date of Patent: September 28, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Chanhee Jeong, Hyunki Kim, Junwoo Park, Byoung Wook Jang, Sunchul Kim, Su-Min Park, Pyoungwan Kim, Inku Kang, Heeyeol Kim
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Publication number: 20200388522Abstract: A bonding apparatus includes a body part; a vacuum hole disposed in the body part; a first protruding part protruding in a first direction from a first surface of the body part; a second protruding part protruding from the first surface of the body part in the first direction and spaced farther apart from a center of the first surface of the body part than the first protruding part in a second direction intersecting with the first direction; and a trench defined by the first surface of the body part and second surfaces of the first protruding part, the second surfaces protruding in the first direction from the first surface of the body part, and the trench being connected to the vacuum hole, wherein the second protruding part protrudes farther from the first surface of the body part in the first direction than the first protruding part.Type: ApplicationFiled: March 2, 2020Publication date: December 10, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Geun AHN, Min Keun KWAK, Ji Won SHIN, Sang Hoon LEE, Byoung Wook JANG
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Patent number: 10622340Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.Type: GrantFiled: November 20, 2017Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chanhee Jeong, Hyunki Kim, Junwoo Park, Byoung Wook Jang, Sunchul Kim, Su-Min Park, Pyoungwan Kim, Inku Kang, Heeyeol Kim
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Publication number: 20200098734Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: CHANHEE JEONG, HYUNKI KIM, JUNWOO PARK, BYOUNG WOOK JANG, SUNCHUL KIM, SU-MIN PARK, PYOUNGWAN KIM, INKU KANG, HEEYEOL KIM
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Patent number: 10510672Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate.Type: GrantFiled: April 18, 2018Date of Patent: December 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uk Kim, Sunchul Kim, Jinkyeong Seol, Byoung Wook Jang
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Publication number: 20190019758Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate.Type: ApplicationFiled: April 18, 2018Publication date: January 17, 2019Inventors: Sang-Uk KIM, Sunchul KIM, Jinkyeong SEOL, BYOUNG WOOK JANG
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Publication number: 20180145061Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.Type: ApplicationFiled: November 20, 2017Publication date: May 24, 2018Inventors: CHANHEE JEONG, HYUNKI KIM, JUNWOO PARK, BYOUNG WOOK JANG, SUNCHUL KIM, SU-MIN PARK, PYOUNGWAN KIM, INKU KANG, HEEYEOL KIM
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Patent number: 9899487Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: GrantFiled: January 12, 2017Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong Lee, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Publication number: 20170263723Abstract: A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.Type: ApplicationFiled: January 12, 2017Publication date: September 14, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Myeong-Dong LEE, Hye-Young Kang, Young-Sin Kim, Yong-Kwan Kim, Byoung-Wook Jang, Augustin Jinwoo Hong, Dong-Sik Kong, Chang-Hyun Cho
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Patent number: 9370098Abstract: Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.Type: GrantFiled: December 15, 2014Date of Patent: June 14, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung Wook Jang, Jongkook Kim, Su-min Park
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Patent number: 9349713Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.Type: GrantFiled: March 25, 2015Date of Patent: May 24, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Kook Kim, Byoung-Wook Jang
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Publication number: 20160027764Abstract: Provided is a semiconductor package stack structure. The semiconductor package stack structure includes a lower semiconductor package, an interposer substrate disposed on the lower semiconductor package and having a horizontal width greater than a horizontal width of the lower semiconductor package, an upper semiconductor package disposed on the interposer substrate, and underfill portions filling a space between the lower semiconductor package and the interposer substrate and surround side surfaces of the lower semiconductor package.Type: ApplicationFiled: March 25, 2015Publication date: January 28, 2016Inventors: Jong-Kook KIM, Byoung-Wook JANG
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Publication number: 20150189750Abstract: Packages substrates are provided. The package substrates may include a substrate and a set of leads disposed on the substrate. The set of lead may include a first lead, a second lead and a third lead, which are sequentially disposed along a first direction. Each of the first lead, the second lead and the third lead may extend along a second direction that is different from the first direction. The first lead and the second lead may be spaced apart at a first distance, and the second lead and the third lead may be spaced apart at a second distance that is less than the first distance.Type: ApplicationFiled: December 15, 2014Publication date: July 2, 2015Inventors: Byoung Wook JANG, Jongkook KIM, Su-min PARK
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Publication number: 20150155216Abstract: A semiconductor chip comprising: a substrate; a plurality of pads disposed on the substrate; and a plurality of passivation patterns laterally separated from each other on the substrate, each of the passivation patterns including a plurality of openings, the openings exposing at least one pad of the pads, and the passivation patterns having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate.Type: ApplicationFiled: September 19, 2014Publication date: June 4, 2015Inventors: JONGKOOK KIM, BYOUNG WOOK JANG
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Patent number: 8847413Abstract: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.Type: GrantFiled: January 15, 2008Date of Patent: September 30, 2014Assignee: STATS ChipPAC Ltd.Inventors: Jae Hak Yee, Byoung Wook Jang
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Patent number: 8810019Abstract: An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die.Type: GrantFiled: February 6, 2012Date of Patent: August 19, 2014Assignee: STATS ChipPAC Ltd.Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang
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Patent number: 8501540Abstract: A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.Type: GrantFiled: June 13, 2011Date of Patent: August 6, 2013Assignee: Stats Chippac Ltd.Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang, YoungChul Kim
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Patent number: 8481420Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity.Type: GrantFiled: March 15, 2011Date of Patent: July 9, 2013Assignee: STATS Chippac Ltd.Inventors: Jong-Woo Ha, DaeSik Choi, Byoung Wook Jang
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Patent number: 8405197Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system.Type: GrantFiled: March 25, 2009Date of Patent: March 26, 2013Assignee: STATS ChipPAC Ltd.Inventors: Jong-Woo Ha, DaeSik Choi, Byoung Wook Jang