Patents by Inventor Byung-hee Kim

Byung-hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7098131
    Abstract: Atomic layers can be formed by introducing a tantalum amine derivative reactant onto a substrate, wherein the tantalum amine derivative has a formula: Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1–C6 alkyl functional group, chemisorbing a portion of the reactant on the substrate, removing non-chemisorbed reactant from the substrate and introducing a reacting gas onto the substrate to form a solid material on the substrate. Thin films comprising tantalum nitride (TaN) are also provided.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 29, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Bom Kang, Byung-Hee Kim, Kyung-In Choi, Gil-Heyun Choi, You-Kyoung Lee, Seong-Geon Park
  • Publication number: 20060167310
    Abstract: The present invention relates to a method for the preparation of naphthalene dicarboxylic acid, and more particularly, to a method for the preparation of naphthalene dicarboxylic acid by oxidizing dimethylnaphthalene with oxygen in air in the presence of acetic acid solvent using the metal catalysts of cobalt and manganese, and using bromine as a reaction initiator, wherein the temperature of said oxidation reaction is 155 to 180° C. The method for the preparation of naphthalene dicarboxylic acid of the invention enables the preparation of naphthalene dicarboxylic acid having high purity with a high yield in an economical way at a low temperature.
    Type: Application
    Filed: May 2, 2003
    Publication date: July 27, 2006
    Inventors: Jong-In Lee, Han-Seok Kim, Byung-Hee Kim, Hang-Duk Roh, Youn-Seo Lee, Joon-Sang Jo
  • Patent number: 7067420
    Abstract: A metal layer is formed on an integrated circuit device including forming an insulating layer on an integrated circuit substrate. A contact hole is formed by selectively etching the insulating layer to thereby partially expose the substrate. A metal layer including tantalum nitride is formed on the insulating layer including the contact hole using a tantalum precursor including a tantalum element and at least one bonding element that is chemically bonded to the tantalum element. A part of the at least one bonding element include at least one ligand bonding element that is ligand-bonded to the tantalum element. Forming the metal layer may include removing at least some of the ligand bonded elements with a removing gas that is substantially free of hydrogen radicals. The metal layer may be formed using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. A copper or other metal layer may be deposited on the metal layer including tantalum nitride.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: June 27, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Gil-Heyun Choi, Byung-Hee Kim, Sang-Bum Kang
  • Patent number: 6981772
    Abstract: An apparatus is provided which maintains alignment of panels in a projector. The apparatus includes a synthesizing system holding device positioned at an upper portion of a synthesizing system of the projector which securely supports the synthesizing system and maintains a relative position of various components of the synthesizing system, even in the event of an external force or vibration applied to the projector. This apparatus can prevent deviation or misalignment between at least two or more prisms and panels in the synthesizing system of the projector, thereby improving reliability and durability of the projector and enhancing image quality.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: January 3, 2006
    Assignee: LG Electronics Inc.
    Inventor: Byung-Hee Kim
  • Publication number: 20050236979
    Abstract: An organic electroluminescence display device comprising a wiring region, including a switching thin film transistor and a driving thin film transistor, and an emission region for emitting light. Light emitted from an organic thin film layer is emitted through the wiring region and the emission region.
    Type: Application
    Filed: April 27, 2005
    Publication date: October 27, 2005
    Inventors: Won-Kyu Kwak, Byung-Hee Kim
  • Patent number: 6955983
    Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: October 18, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo
  • Patent number: 6951814
    Abstract: Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 4, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-hee Kim, Gil-heyun Choi, Ju-young Yun, Jung-hun Seo
  • Publication number: 20050200617
    Abstract: Red, green, and blue organic electroluminescent (EL) elements formed on a pixel in an organic EL display are driven by a driving transistor. A capacitor is coupled between a gate and a source of the driving transistor to maintain a voltage for a predetermined time. Emission control transistors are coupled between the driving transistor and the red, green, and blue organic EL elements, respectively. One field is divided into three subfields, and one of the red, green and blue organic EL elements in each pixel starts to emit light in each subfield to thus represent a full color screen. The red, green and blue organic elements sequentially start to emit light in each subfield such that a color separation phenomenon caused by start emitting organic EL elements of one color during each subfield is reduced or eliminated.
    Type: Application
    Filed: February 10, 2005
    Publication date: September 15, 2005
    Inventors: Won-Kyu Kwak, Byung-Hee Kim
  • Publication number: 20050179141
    Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 18, 2005
    Inventors: Ju-young Yun, Gil-heyun Choi, Byung-hee Kim, Jong-myeong Lee, Seung-gil Yang, Jung-hun Seo
  • Patent number: 6929956
    Abstract: A ferroelectric random access memory (FRAM) device, and a fabrication method therefor, includes seed layers above and below a ferroelectric layer. The seed layers formed above and below faces of the ferroelectric layer can prevent an imprint phenomenon from being generated in a ferroelectric capacitor by making the characteristics of the upper and lower interfaces of the ferroelectric layer be the same. This is accomplished by providing upper and lower seed layers that are crystallized prior to the ferroelectric layer during a thermal treatment. This results in crystallization occurring from the upper and lower faces to the center of the ferroelectric layer, making the characteristics of the upper and lower interfaces of the ferroelectric layer the same, thereby improving ferroelectric capacitor characteristics.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-hee Kim, Hong-bae Park
  • Publication number: 20050136652
    Abstract: A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.
    Type: Application
    Filed: January 28, 2005
    Publication date: June 23, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hee Kim, Gil-Heyun Choi, Kyung-In Choi
  • Publication number: 20050110403
    Abstract: A flat panel display comprises: a transparent substrate having a first display portion and a second display portion; at least one first organic light emitting diode positioned in the first display portion for emitting light in a first direction perpendicular to the transparent substrate, and having a first lower electrode, a first upper electrode, and a first organic emission layer interposed between the first lower electrode and the first upper electrode; and at least one second organic light emitting diode positioned in the second display portion for emitting light in a second direction opposite to the first direction, and having a second lower electrode, a second upper electrode, and a second organic emission layer interposed between the second lower electrode and the second upper electrode. As a result, the flat panel display is fabricated using one substrate to display both screens such that one of the screens is displayed while the other is not displayed.
    Type: Application
    Filed: November 4, 2004
    Publication date: May 26, 2005
    Inventors: Dong-Won Han, Byung-Hee Kim
  • Publication number: 20050082625
    Abstract: Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 21, 2005
    Inventors: Byung-Hee Kim, Gil-Heyun Choi, Kyung-In Choi, Chang-Won Lee
  • Patent number: 6876078
    Abstract: A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hee Kim, Gil-Heyun Choi, Kyung-In Choi
  • Patent number: 6871960
    Abstract: Disclosed is a cooling system for a projector which is capable of more quickly exhaust the hot air generated in the interior of the projector. A cooling system for a projector comprising a suction fan placed at the top of a synthesizing system of the projector, a fan guide fastened at a surface between the top of the synthesizing system and the bottom of the suction fan, the fan guide having a configuration in which one end is shorter the other so that the suction fan is place in a incline position to allow the hot air to be rapidly exhausted.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: March 29, 2005
    Assignee: LG Electronics Inc.
    Inventor: Byung Hee Kim
  • Publication number: 20050057461
    Abstract: A flat panel display device in which a cathode line and a power line are arranged such that voltage drops therein compensate each other. The flat panel display device of the present invention includes an insulating substrate having a pixel region in which pixels are arranged; a power line for supplying a power supply voltage to the pixels; and a cathode electrode having a cathode contact for supplying a cathode voltage to the pixels, wherein an input side of the power line and the cathode contact of the cathode electrode are arranged on the substrate opposite each other with respect to the pixel region. The cathode electrode further includes a cathode bus line for applying an external cathode voltage, the cathode electrode being in contact with the cathode bus line via the cathode contact to provide the external cathode voltage to the pixels.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 17, 2005
    Inventors: Mi-Sook Suh, Byung-Hee Kim
  • Patent number: 6849555
    Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 1, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-myeong Lee, Byung-hee Kim, Myoung bum Lee, Ju-young Yun, Gil-heyun Choi
  • Publication number: 20040251823
    Abstract: A double-sided light emitting device including lower and upper substrates, an emission element formed between an inner surface of the upper substrate and an inner surface of the lower substrate and emitting predetermined light, an upper layer of polarizing material disposed on at least one of inner and outer surfaces of the upper substrate, and a lower layer of polarizing material disposed on at least one of inner and outer surfaces of the lower substrate.
    Type: Application
    Filed: May 20, 2004
    Publication date: December 16, 2004
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Jin-Woo Park, Ho-Kyoon Chung, Sun-Hwa Kim, Byung-Hee Kim
  • Publication number: 20040224506
    Abstract: Methods of forming metal layers include techniques to form metal layers using atomic layer deposition techniques that may be repeated in sequence to build up multiple atomic metal layers into a metal thin film. The methods include forming a metal layer by chemisorbing a metallic precursor comprising a metal element and at least one non-metal element that is ligand-bonded to the metal element, on a substrate. The metal element may include tantalum. The chemisorbed metallic precursor is then converted into the metal layer by removing the at least one non-metal element from the metallic precursor through ligand exchange. This removal of the non-metal element may be achieved by exposing the chemisorbed metallic precursor to an activated gas that is established by a remote plasma, which reduces substrate damage. The activated gas may be selected from the group consisting of H2, NH3, SiH4 and Si2H6 and combinations thereof. These steps may be performed at a temperature less than about 650° C.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Inventors: Kyung-In Choi, Sang-Bum Kang, Byung-Hee Kim, Gil-Heyun Choi
  • Patent number: D519582
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: April 25, 2006
    Inventor: Byung-Hee Kim