Abstract: An ultra-wideband (UWB) receiver utilizing an Xn(n>1) device as a signal detector for short pulse(s), impulse(s) or ultra-wideband signal(s). The transmitted signal comes to antenna and passes through a band pass filter (BPF). The signal is fed into an Xn device. The output signal from the Xn device is fed into integration/dump block. The output from the integration/dump block is fed into decision block.

Abstract: A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

Abstract: An ultra-wideband (UWB) receiver utilizing an Xn(n>1) device as a signal detector for short pulse(s), impulse(s) or ultra-wideband signal(s). The transmitted signal comes to antenna and passes through a band pass filter (BPF). The signal is fed into an Xn device. The output signal from the Xn device is fed into integration/dump block. The output from the integration/dump block is fed into decision block.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: Disclosed is a display device (e.g., a liquid crystal display), and an apparatus and a method for driving the display device. The LCD includes an LCD panel having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode each connected to one of the data lines; a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and a data driver for dividing the data lines into a certain number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block. The apparatus includes the gate driver and the data driver.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: The present invention modifies LCD panel display modes with a simple circuit configuration. When a driving frequency is supplied that does not drive all the configured pixels, the present invention drives all the pixels according to a multisync mode. The present invention comprises a LCD panel including a plurality of gate lines, a plurality of data lines, and a plurality of TFTs each having a gate electrode connected to the gate line and having a source electrode connected to the data line; a data driver receiving four driving clock signals and performing a multisync function on the driving frequency; a gate driver receiving four shift clock signals and performing multisync function on the driving frequency; and a timing controller outputting four driving clock signals and shift clocks and changing and outputting the status of the four driving clock signal and the shift clocks according to the normal mode or multisync mode.

Abstract: A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Abstract: Disclosed is a display device (e.g., a liquid crystal display), and an apparatus and a method for driving the display device. The LCD includes an LCD panel having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode each connected to one of the data lines; a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and a data driver for dividing the data lines into a certain number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block. The apparatus includes the gate driver and the data driver.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A sealant pattern is interposed between an upper substrate having a common electrode and a lower substrate having a display area and driving circuits, and surrounds the display area. A liquid crystal layer is formed between the two substrates and inside the display area. Since the liquid crystal layer is not interposed between the driving circuits and the common electrode, a parasitic capacitance generated between bus lines of the driving circuits and the common electrode can be reduced. Moreover, it is possible to form an additional sealant pattern surrounding the driving circuits and inject a material having a lower dielectric constant than the liquid crystal into a region sealed off by the two sealant patterns.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A plurality of gate lines transmits scanning signals are formed on a substrate and a plurality of storage electrode lines are formed in parallel to the gate lines. The storage electrode lines and the gate lines are alternately arranged. A plurality of data lines transmitting image signals intersect the gate lines and the storage electrode lines with being insulated therefrom and a plurality of pixel electrodes are formed. The pixel electrode, which is connected to the thin film transistor which is turned on or off by the nth gate line 110, overlaps the nth and the (n−1)th storage electrode lines 210 which are respectively placed between the nth and the (n−1)th gate lines and between the (n−1)th and the (n 2)th gate lines, and the (n−1)th gate line 110. Therefore, abnormal electric field near the edges of the pixel electrodes is covered by the storage electrode lines and the gate lines.

Abstract: A method for fabricating a thin film transistor includes the steps of calculating a scan pitch of a laser beam such that an unevenly crystallized area and an evenly crystallized area of a crystallized polycrystalline silicon layer are alternately arranged at a regular interval, crystallizing an amorphous silicon layer to a polycrystalline silicon layer by scanning the laser beam according to the scan pitch, calculating a spacing pitch of active patterns from the scan pitch of the laser beam, and forming the active patterns in a selected portion of the polycrystalline silicon layer according to the spacing pitch.