Patents by Inventor Byung-Hoon Jeong

Byung-Hoon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220173204
    Abstract: A display device is disclosed, and the display device includes a substrate including first to third display regions, the second and the third display regions being spaced from each other, each of the second and third display regions having an area smaller than that of the first display region and being continuous to the first display region, first to third pixels in the first to third display regions, first to third lines connected to the first to third pixels, and a dummy part configured to compensate for a difference between a load value of the first lines and load values of the second and third lines, wherein the second display region includes a first sub-region adjacent to the first display region and a second sub-region spaced from the first display region, and the third display region includes a third sub-region adjacent to the first display region and a fourth sub-region spaced from the first display region.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: Hyung Jun PARK, Yang Wan KIM, Byung Sun KIM, Su Jin LEE, Jae Yong LEE, Ji Hyun KA, Tae Hoon KWON, Jin Tae JEONG, Seung Ji CHA
  • Patent number: 11340304
    Abstract: A method for charging a battery may include: obtaining a state of health of the battery and a magnitude of an initial charging current preset for the battery; converting the magnitude of the initial charging current on the basis of the state of health of the battery, thereby generating a charging current command; and providing the charging current command to a charger, and supplying a charging current corresponding to the charging current command to the battery by the charger.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 24, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Yoon Jun Lee, Byung Jo Jeong, Jae Hoon Choi
  • Publication number: 20220153030
    Abstract: The present invention provides an apparatus for treating a substrate, the apparatus including: a head unit including a head formed with one or more nozzles that discharge a treatment liquid to a substrate; and a head maintenance unit configured to perform maintenance for the head, in which the head maintenance unit may include: a liquid receiving block formed with one or more liquid receiving parts having liquid receiving spaces with open tops; a decompression line fluidly-communicating with the liquid receiving space and configured to provide reduced pressure to the liquid receiving space; and a decompression valve installed in the decompression line.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 19, 2022
    Inventors: Byung Joo LEE, Sang Hwa LEE, Dong Yun LEE, Jee Yong JUNG, Hahn Seok JEON, Kang KWON, Jae Hun JEONG, Sang Hoon KIM
  • Publication number: 20220122675
    Abstract: A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.
    Type: Application
    Filed: July 19, 2021
    Publication date: April 21, 2022
    Inventors: TongSung KIM, Dae Hoon NA, Jung-June PARK, Dong Ho SHIN, Byung Hoon JEONG, Young Min JO
  • Patent number: 11257531
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Publication number: 20210391023
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
  • Publication number: 20210320039
    Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Min-Jae LEE, Sang-Lok KIM, Byung-Hoon JEONG, Tae-Sung LEE, Jeong-Don IHM, Jae-Yong JEONG, Young-Don CHOI
  • Patent number: 11114171
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
  • Patent number: 11062966
    Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 13, 2021
    Inventors: Min-Jae Lee, Sang-Lok Kim, Byung-Hoon Jeong, Tae-Sung Lee, Jeong-Don Ihm, Jae-Yong Jeong, Young-Don Choi
  • Publication number: 20210201964
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 1, 2021
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 11024400
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20210151117
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Publication number: 20210151089
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 20, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10964360
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10937474
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10937471
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10916315
    Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Woo Yu, Sang Lok Kim, Byung Kwan Chun, Byung Hoon Jeong, Jeong Don Ihm, Young Don Choi
  • Publication number: 20200402592
    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
  • Publication number: 20200379862
    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 3, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Jung, Jang-woo Lee, Byung-hoon Jeong, Jeong-don Ihm
  • Publication number: 20200349986
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi