Patents by Inventor Byung-Hoon Jeong

Byung-Hoon Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050281114
    Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.
    Type: Application
    Filed: September 27, 2004
    Publication date: December 22, 2005
    Inventors: Hyung-Chan Choi, Chi-Wook Kim, Byung-Hoon Jeong
  • Publication number: 20050253631
    Abstract: We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 17, 2005
    Inventors: Chul-Soo Kim, Byung-Hoon Jeong
  • Publication number: 20050248042
    Abstract: A semiconductor memory device having a memory cell array includes a plurality of first signal lines arranged on the memory cell array in the same direction and a plurality of second signal lines arranged on the memory cell array in a perpendicular direction to the first signal lines. The first signal lines are alternately arranged on at least two layers, and the second signal lines are arranged on a layer where the first signal lines are not arranged.
    Type: Application
    Filed: May 4, 2005
    Publication date: November 10, 2005
    Inventors: Jong-Eon Lee, Chul-Soo Kim, Byung-Hoon Jeong, Jun-Hyung Kim, Young-Sun Min
  • Patent number: 6944089
    Abstract: Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 13, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hoon Jeong, Woo-Seop Jeong, Byung-Chul Kim, Beob-Rae Cho, Seung-Bum Ko
  • Publication number: 20050141334
    Abstract: A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 30, 2005
    Inventor: Byung-Hoon Jeong
  • Publication number: 20040108877
    Abstract: A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal.
    Type: Application
    Filed: November 18, 2003
    Publication date: June 10, 2004
    Inventors: Geun-Hee Cho, Byung-Hoon Jeong, Kyu-Hyoun Kim
  • Publication number: 20030210604
    Abstract: Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.
    Type: Application
    Filed: December 31, 2002
    Publication date: November 13, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hoon Jeong, Woo-Seop Jeong, Byung-Chul Kim, Beob-Rae Cho, Seung-Bum Ko