Abstract: NCAPG2, a component of condensin complex II, protein and novel peptides derived from the protein are provided. The peptide may include a fragment of the NCAPG2 protein. The peptide may be a peptide including a fragment of NCAPG2 protein having the amino acid sequence of SEQ ID NO: 7, wherein the fragment includes the amino acid residue number 805 or 1010 of SEQ ID NO: 7, a peptide having the sequence of SEQ ID NO: 8, or a peptide having the sequence of SEQ ID NO: 11. The protein or peptides can be used for preparing and screening pharmaceutical compositions for treating diseases or disorders associated with abnormal cell division including cancer.

Abstract: NCAPG2, a component of condensin complex II, protein and novel peptides derived from the protein are provided. The peptide may include a fragment of the NCAPG2 protein. The peptide may be a peptide including a fragment of NCAPG2 protein having the amino acid sequence of SEQ ID NO: 7, wherein the fragment includes the amino acid residue number 805 or 1010 of SEQ ID NO: 7, a peptide having the sequence of SEQ ID NO: 8, or a peptide having the sequence of SEQ ID NO: 11. The protein or peptides can be used for preparing and screening pharmaceutical compositions for treating diseases or disorders associated with abnormal cell division including cancer.

Abstract: Substrate heat treatment apparatus and method are provided. According to an embodiment of the present invention, there is provided a substrate heat treatment apparatus including an inner shell configured to form a substrate housing space to house at least one substrate, an outer shell configured to cover the inner shell, and having at least one gas hole, and at least one heater configured to heat the substrate, wherein the at least one gas hole is configured to allow a first gas to be injected into a space between the inner shell and the outer shell.

Abstract: Provided is a reactor of a substrate processing apparatus. The reactor of the substrate processing apparatus is a reactor of a substrate processing apparatus for processing at least one substrate, the reactor having a horizontal cross-section provided in a shape having at least two curvature radii.

Abstract: NCAPG2, a component of condensin complex II, protein and novel peptides derived from the protein are provided. The peptide may include a fragment of the NCAPG2 protein. The peptide may be a peptide including a fragment of NCAPG2 protein having the amino acid sequence of SEQ ID NO: 7, wherein the fragment includes the amino acid residue number 805 or 1010 of SEQ ID NO: 7, a peptide having the sequence of SEQ ID NO: 8, or a peptide having the sequence of SEQ ID NO: 11. The protein or peptides can be used for preparing and screening pharmaceutical compositions for treating diseases or disorders associated with abnormal cell division including cancer.

Abstract: Substrate heat treatment apparatus and method are provided. According to an embodiment of the present invention, there is provided a substrate heat treatment apparatus including an inner shell configured to form a substrate housing space to house at least one substrate, an outer shell configured to cover the inner shell, and having at least one gas hole, and at least one heater configured to heat the substrate, wherein the at least one gas hole is configured to allow a first gas to be injected into a space between the inner shell and the outer shell.

Abstract: The present invention relates to ethacrynic acid and a transglutaminase inhibitor comprising a pharmaceutically acceptable salt of ethacrynic acid; more particularly, to ethacrynic acid for inhibiting the activity of transglutaminase involved in the pathogenesis of diseases in cases of altered expression, a transglutaminase inhibitor comprising a pharmaceutically acceptable salt of ethacrynic acid, and to a novel use of thereof. According to the present invention, there are provided ethacrynic acid, a transglutaminase inhibitor comprising active components of a pharmaceutically acceptable salt of ethacrynic acid and a transglutaminase inhibition method.

Abstract: A semiconductor manufacturing apparatus includes: a reaction chamber for providing an airtight process space; a boat for loading/unloading a pair of semiconductor substrates into/from the reaction chamber, wherein the boat includes susceptors and rotary tables to be rotatably supported by a plurality of supporting rollers, each semiconductor substrate being mounted onto each susceptor and each susceptor being mounted onto each rotary table, respectively; heaters, arranged at backsides of the semiconductor substrates, for performing an epitaxial process in the reaction chamber; a process gas nozzle, installed to encircle an upper fringe of the semiconductor substrates; an exhaust gas nozzle, installed to encircle a lower fringe of the semiconductor substrates; and a purge gas nozzle for supplying a purge gas capable of preventing an outer wall of the process gas nozzle from being deposited, wherein the purge gas nozzle is arranged near to the process gas nozzle.

Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconductor device on a semi conductor substrate forming an insulating layer on the transistor; forming contact holes, through which a region of the transistor is exposed, by selectively removing the insulating layer forming a silicon layer in the contact holes forming a metal layer on the insulating layer and the silicon layer; forming a metal suicide layer through heat treatment of the silicon layer and the metal layer; removing the metal layer; forming an amorphous silicon layer on the insulating layer and the metal suicide layer; and forming a polysilicon layer through heat treatment of the amorphous silicon layer.

Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).

Abstract: A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d).

Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on.

Abstract: A semiconductor manufacturing system and wafer holder for a semiconductor manufacturing system which prevents a semiconductor wafer from being exposed to a process reaction and which includes a reaction tube for providing a sealed process space and a dual boat and which prevents the backside deposition by the wafer holder. The wafer holder includes a holder body to hide the backside of the semiconductor wafer during a process in the reaction tube and a wafer lifter having a portion that can be disengaged from and coupled to the holder body so that a lower portion of the semiconductor wafer is supported by the dual boat and so that the semiconductor wafer can be lifted up from the wafer body when the semiconductor wafer is loaded and unloaded. A separation boundary between the holder body and the wafer lifter includes a gas inflow interception surface to hinder reaction gas from flowing through the separation boundary.

Abstract: System for visualizing conductivity and current density distributions including a plurality of current injecting devices (100) for injecting currents into a measuring object; a measuring unit (200) for measuring a magnetic flux density due to the currents injected into a measuring object; an operating unit (300) for selecting one pair of the current injecting devices in succession so as to inject currents of different directions into the measuring object, and calculating directional components of an anisotropic conductivity inside of the measuring object on the basis of the measured magnetic flux density; and displaying means for visualizing an inside of the measuring object by using the calculated directional components of the anisotropic conductivity.

Abstract: A semiconductor manufacturing system and wafer holder for a semiconductor manufacturing system which prevents a semiconductor wafer from being exposed to a process reaction and which includes a reaction tube for providing a sealed process space and a dual boat and which prevents the backside deposition by the wafer holder. The wafer holder includes a holder body to hide the backside of the semiconductor wafer during a process in the reaction tube and a wafer lifter having a portion that can be disengaged from and coupled to the holder body so that a lower portion of the semiconductor wafer is supported by the dual boat and so that the semiconductor wafer can be lifted up from the wafer body when the semiconductor wafer is loaded and unloaded. A separation boundary between the holder body and the wafer lifter includes a gas inflow interception surface to hinder reaction gas from flowing through the separation boundary.

Abstract: An apparatus and method for wet pre-treatment of an effluent gas derived from upstream semiconductor or LCD manufacturing tools before the effluent gas is processed in an effluent gas treatment system in provided. The apparatus comprises an atomizing spray nozzle for atomizing a reagent and a processing section in which the effluent gas in pre-treated with the atomized reagent using a cyclone method. The processing section comprises an inner tubular portion and an outer tubular portion. The processing section has an effluent gas inlet, a reagent inlet, an effluent gas outlet, and a waste liquid outlet. An apparatus is also provided which includes a plurality of wet pre-treatment units, each of which pre-treat each of effluent gas streams derived from a plurality of CVD chambers.

Abstract: The present invention discloses a semiconductor wafer baking apparatus comprising a heating plate, a wafer guide, and an exhaust heat compensator. The heating plate is loaded with a wafer and the wafer guide arranges the wafer on the heating plate. The exhaust heat compensator is placed on the wafer guide and compensates exhausted heat from an edge area of the wafer. The exhaust heat compensator comprises a penetration hole to expose a center portion of the wafer. Therefore, the semiconductor wafer baking apparatus according to the present invention compensates the heat loss occurring in the edge area of the wafer and keeps the edge area of the wafer from temperature drop, which results in a temperature uniformity on the wafer surface. By reducing the temperature deviation within a wafer, a uniform pattern size of an entire wafer in the semiconductor wafer manufacturing process is achieved so that the process reliability and the process yields can be improved.

Abstract: The present invention discloses a semiconductor wafer baking apparatus comprising a heating plate, a wafer guide, and an exhaust heat compensator. The heating plate is loaded with a wafer and the wafer guide arranges the wafer on the heating plate. The exhaust heat compensator is placed on the wafer guide and compensates exhausted heat from an edge area of the wafer. The exhaust heat compensator comprises a penetration hole to expose a center portion of the wafer. Therefore, the semiconductor wafer baking apparatus according to the present invention compensates the heat loss occurring in the edge area of the wafer and keeps the edge area of the wafer from temperature drop, which results in a temperature uniformity on the wafer surface. By reducing the temperature deviation within a wafer, a uniform pattern size of an entire wafer in the semiconductor wafer manufacturing process is achieved so that the process reliability and the process yields can be improved.

Abstract: A device for writing a data in a non-volatile memory circuit having a plurality of memory cells includes an input/output port inputting and outputting an address and the data, a first decoder decoding the address from the input/output port and outputting a first decoded data, a second decoder decoding the data from the input/output port, sequentially determining a block value corresponding to the address from the input/output port, and outputting a second decoded data, a data processing part receiving and processing the second decoded data from the second decoder and outputting an address bit value, a first DEMUX receiving the address bit value from the data processing part and outputting a demultiplexed data corresponding to the block value determined in the second decoder, a NOR gate part receiving the first decoded data from the first decoder and the demultiplexed data from the first DEMUX, and outputting a signal having a logical NOR result, a second DEMUX receiving an output signal from the data processi

Abstract: A variable threshold voltage adjustment circuit for a semiconductor device includes a transistor for supplying a first voltage in response to a first data signal, a program unit for outputting a multi-stage voltage in response to the first data signal and a second data signal, and a nonvolatile memory device connected to the transistor and having a logic threshold voltage corresponding to the multi-stage voltage of the program unity.