Abstract: A non-volatile semiconductor memory device and manufacturing methods therefor, in which the control gate and floating gate are formed in the form of a single level or planar polysilicon layer so as to solve the problem of step coverage. The floating gate is formed in a self-aligning manner. The method may include the steps of: (a) forming a control gate upon an insulated semiconductor substrate; (b) forming an insulating layer upon the control gate; (c) depositing a polysilicon on the entire surface, etching back the polysilicon, and forming side wall floating gates on sides of the control gate; and (d) doping the substrate using the control gate and the side wall floating gates as masks so as to form source and drain regions.

Abstract: A method for forming of a semiconductor device having a transistor with a floating gate includes the steps of forming a first insulating layer and a first conductive layer on a surface of the substrate, patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes and implanting ions on the cell forming area, forming a second insulating layer on the resulting surface so that the second insulating layer fills a space between the preliminary floating gate electrodes, forming a third insulating layer on the resulting surface, forming a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second conductive layer, forming a gate electrode by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode pattern has a first distance between the gate lines in a portion to be a contact hole, and a second distance between the gate lines is arranged in another portion, the first distance being wide