Abstract: An airbag device and a method for controlling deployment of the same are proposed. The airbag device is configured to protect a passenger by controlling an airbag cushion deployed toward the rear space of a seatback in an event of a vehicle collision, and the airbag device includes an airbag cushion deploying toward the rear space of the seatback, a sensor part detecting a seating status and a seating posture of a passenger with respect to each seat, and a controller, in an event of a collision, configured to change and control a deploying status of the airbag cushion and an inflation amount of the airbag cushion in response to the seating status and the seating posture of the passenger.

Abstract: Disclosed are a shoulder airbag and an airbag cushion thereof that are capable of restricting an occupant from being moved upward along a seatback and from being abruptly pushed in a direction away from a collision side of a vehicle when vehicle collision occurs, thereby safely protecting the occupant. The shoulder airbag includes an airbag cushion mounted in a seatback and configured to be deployed so as to cover each of the shoulders of an occupant sitting in a seat in three axis directions.

Abstract: An embodiment comprises: a housing comprising side parts, a first corner part, a second corner part, a third corner part, and a fourth corner part, in which each of the first corner part, the second corner part, the third corner part and the fourth corner is disposed between two adjacent side parts; a bobbin disposed in the housing; a first coil disposed on an outer surface of the bobbin; first magnets disposed on the side parts of the housing; a first circuit board disposed on the first corner part and comprising a first pad, a second pad, a third pad, a fourth pad, a fifth pad and a sixth pad; a first location sensor disposed on the first circuit board and electrically connected to the first pad, the second pad, the third pad, the fourth pad, the fifth pad and the sixth pad; first, second, third and fourth upper springs disposed apart from each other on the housing; and first and second lower springs coupled to a lower portion of the housing, electrically connected with the first coil, and coupled to the fi

Abstract: A self-healing alloy contains 5 to 11% by weight of molybdenum (Mo), iron (Fe) as a remainder, and unavoidable impurities. A method for manufacturing the self-healing alloy includes heat treating the alloy or preparing an alloy raw material powder and sintering, homogenizing, and cooling the alloy raw material powder.

Abstract: In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

Abstract: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: Disclosed herein is a PET-MRI combination apparatus which can extend transaxial and axial fields of view (FOV) by transmitting an output signal from a photo sensor to the outside of an MRI bore using cable. The PET-MRI combination apparatus includes an MRI bore for capturing an MR image of an object. A PET detector is installed inside imaging space of the MRI bore, and is configured such that a plurality of scintillation crystal arrays, each having scintillation crystals arranged in a ring shape, is arranged in a longitudinal direction so as to extend a axial field of view (FOV). A PET circuit unit is installed outside the MRI bore to prevent the PET circuit unit from being influenced by a magnetic field in the MRI bore, and is configured to include a signal amplification circuit and a signal processing circuit. A cable is configured to connect the PET detector to the PET circuit unit.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

Abstract: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.

Abstract: A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: Disclosed herein is a PET-MRI combination apparatus which can extend transaxial and axial fields of view (FOV) by transmitting an output signal from a photo sensor to the outside of an MRI bore using cable. The PET-MRI combination apparatus includes an MRI bore for capturing an MR image of an object. A PET detector is installed inside imaging space of the MRI bore, and is configured such that a plurality of scintillation crystal arrays, each having scintillation crystals arranged in a ring shape, is arranged in a longitudinal direction so as to extend a axial field of view (FOV). A PET circuit unit is installed outside the MRI bore to prevent the PET circuit unit from being influenced by a magnetic field in the MRI bore, and is configured to include a signal amplification circuit and a signal processing circuit. A cable is configured to connect the PET detector to the PET circuit unit.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

Abstract: A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

Abstract: A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.