Patents by Inventor Byung-Kwan You
Byung-Kwan You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968835Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: GrantFiled: March 14, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Publication number: 20220199642Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Patent number: 11276709Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: GrantFiled: July 20, 2020Date of Patent: March 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Patent number: 11145672Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.Type: GrantFiled: December 7, 2019Date of Patent: October 12, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Boh Chang Kim, Chung Ki Min, Ji Hoon Park, Byung Kwan You
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Publication number: 20210005628Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: ApplicationFiled: July 20, 2020Publication date: January 7, 2021Inventors: Eun-Taek JUNG, Joong-Shik SHIN, Byung-Kwan YOU
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Patent number: 10854632Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.Type: GrantFiled: December 30, 2019Date of Patent: December 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Young-Hwan Son, Byung-Kwan You, Eun-Taek Jung
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Patent number: 10741575Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: GrantFiled: August 28, 2018Date of Patent: August 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Publication number: 20200144288Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.Type: ApplicationFiled: December 30, 2019Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Young-Hwan Son, Byung-Kwan You, Eun-Taek Jung
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Publication number: 20200119044Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.Type: ApplicationFiled: December 7, 2019Publication date: April 16, 2020Inventors: SEOK CHEON BAEK, BOH CHANG KIM, CHUNG KI MIN, JI HOON PARK, BYUNG KWAN YOU
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Patent number: 10559591Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.Type: GrantFiled: August 31, 2018Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Young-Hwan Son, Byung-Kwan You, Eun-Taek Jung
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Patent number: 10553609Abstract: A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.Type: GrantFiled: October 2, 2018Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Woong Seop Lee, Byung Kwan You, Jae Woo Kwak
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Patent number: 10535679Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.Type: GrantFiled: September 20, 2018Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok Cheon Baek, Boh Chang Kim, Chung Ki Min, Ji Hoon Park, Byung Kwan You
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Publication number: 20190304992Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.Type: ApplicationFiled: September 20, 2018Publication date: October 3, 2019Inventors: SEOK CHEON BAEK, BOH CHANG KIM, CHUNG KI MIN, JI HOON PARK, BYUNG KWAN YOU
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Publication number: 20190237476Abstract: A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.Type: ApplicationFiled: October 2, 2018Publication date: August 1, 2019Inventors: Woong Seop Lee, Byung Kwan You, Jae Woo Kwak
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Publication number: 20190157294Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.Type: ApplicationFiled: August 31, 2018Publication date: May 23, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji KANAMORI, Young-Hwan SON, Byung-Kwan YOU, Eun-Taek JUNG
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Publication number: 20190148399Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.Type: ApplicationFiled: August 28, 2018Publication date: May 16, 2019Inventors: Eun-Taek Jung, Joong-Shik Shin, Byung-Kwan You
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Patent number: 9202932Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.Type: GrantFiled: March 15, 2013Date of Patent: December 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Woo Paek, Jung-Dal Choi, Young-Seop Rah, Byung-Kwan You, Seok-Won Lee
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Patent number: 9171729Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.Type: GrantFiled: March 7, 2014Date of Patent: October 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan You, Kwang-Soo Seol, Young-woo Park, Jin-Soo Lim
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Publication number: 20150060993Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: ApplicationFiled: October 31, 2014Publication date: March 5, 2015Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Lee, Sang-yong Park
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Patent number: 8877626Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: GrantFiled: May 17, 2013Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Lee, Sang-yong Park