Patents by Inventor Byung-Kwan You
Byung-Kwan You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8877626Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: GrantFiled: May 17, 2013Date of Patent: November 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Lee, Sang-yong Park
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Patent number: 8836074Abstract: A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.Type: GrantFiled: December 27, 2012Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan You, Seung-Woo Paek, Chung-Il Hyun, Jung-Dal Choi
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Publication number: 20140193966Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.Type: ApplicationFiled: March 7, 2014Publication date: July 10, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan YOU, Kwang-Soo SEOL, Young-Woo PARK, Jin-Soo LIM
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Patent number: 8697524Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.Type: GrantFiled: August 18, 2011Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan You, Kwang-Soo Seol, Young-Woo Park, Jin-Soo Lim
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Publication number: 20130256781Abstract: In a method of manufacturing a semiconductor device, a dielectric layer structure and a control gate layer can be formed sequentially on a substrate. The control gate layer can be partially etched to form a plurality of control gates. A gate spacer and a sacrificial spacer sequentially can be stacked on a sidewall of the control gate and on a portion of the dielectric layer structure. The dielectric layer structure can be partially etched using the sacrificial spacer and the gate spacer as an etching mask to form a plurality of dielectric layer structure patterns. The sacrificial spacer can be removed. An insulating interlayer can be formed on the substrate to form an air gap. The insulating interlayer can cover the dielectric layer structure pattern, the gate spacer and the control gate. The air gap can extend between the adjacent gate spacers and between the adjacent dielectric layer structure patterns.Type: ApplicationFiled: March 15, 2013Publication date: October 3, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Seung-Woo PAEK, Jung-Dal Choi, Young-Seop Rah, Byung-Kwan You, Seok-Won Lee
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Publication number: 20130252391Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: ApplicationFiled: May 17, 2013Publication date: September 26, 2013Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Lee, Sang-yong Park
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Patent number: 8455940Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: GrantFiled: May 4, 2011Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Lee, Sang-yong Park
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Patent number: 8178442Abstract: A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively.Type: GrantFiled: July 13, 2009Date of Patent: May 15, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Jae-kwan Park, Dong-hwa Kwak, Byung-kwan You
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Publication number: 20120058629Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.Type: ApplicationFiled: August 18, 2011Publication date: March 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Kwan You, Kwang-Soo Seol, Young-Woo Park, Jin-Soo Lim
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Publication number: 20110287612Abstract: A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.Type: ApplicationFiled: May 4, 2011Publication date: November 24, 2011Inventors: Jae-goo Lee, Young-woo Park, Byung-kwan You, Dong-sik Iee, Sang-yong Park
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Publication number: 20100093173Abstract: A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively.Type: ApplicationFiled: July 13, 2009Publication date: April 15, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yong PARK, Jae-kwan PARK, Dong-hwa KWAK, Byung-kwan YOU
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Patent number: 7608500Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.Type: GrantFiled: February 6, 2007Date of Patent: October 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Kwan You, Jun-Eui Song, Gyeong-Hee Kim, Hee-Jueng Lee
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Publication number: 20070184606Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.Type: ApplicationFiled: February 6, 2007Publication date: August 9, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byung-Kwan YOU, Jun-Eui SONG, Gyeong-Hee KIM, Hee-Jueng LEE
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Patent number: 6818510Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region.Type: GrantFiled: November 6, 2003Date of Patent: November 16, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byung-Kwan You, Sung-Hoi Hur
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Publication number: 20040094776Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region.Type: ApplicationFiled: November 6, 2003Publication date: May 20, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byung-Kwan You, Sung-Hoi Hur
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Patent number: 6677639Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region.Type: GrantFiled: July 1, 2002Date of Patent: January 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byung-Kwan You, Sung-Hoi Hur
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Publication number: 20030017671Abstract: A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region.Type: ApplicationFiled: July 1, 2002Publication date: January 23, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Lee, Jung-Dal Choi, Byung-Kwan You, Sung-Hoi Hur