Patents by Inventor Byung-Lyul Park

Byung-Lyul Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME
    Publication number: 20150137326
    Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 21, 2015
    Inventors: Pil-Kyu KANG, Byung Lyul PARK, SungHee KANG, TAESEONG KIM, TAEYEONG KIM, KWANGJIN MOON, Jae-Hwa PARK, SUKCHUL BANG, Seongmin SON, JIN HO AN, Ho-Jin LEE, JEONGGI JIN
  • SEMICONDUCTOR DEVICE HAVING METAL PATTERNS AND PIEZOELECTRIC PATTERNS
    Publication number: 20150137325
    Abstract: Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.
    Type: Application
    Filed: July 11, 2014
    Publication date: May 21, 2015
    Inventors: Yi-Koan HONG, Byung-Lyul PARK, Ji-Soon PARK, Si-Young CHOI
  • SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURES INCLUDING THE SAME
    Publication number: 20150132950
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Deok-young JUNG, Pil-kyu KANG, Byung-lyul PARK, Ji-soon PARK, Seong-min SON, Jin-ho AN, Ji-hwang KIM
  • SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE
    Publication number: 20150129978
    Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.
    Type: Application
    Filed: July 8, 2014
    Publication date: May 14, 2015
    Inventors: KWANG-JIN MOON, BYUNG-LYUL PARK, JAE-HWA PARK
  • Integrated circuit having through silicon via structure with minimized deterioration
    Patent number: 9018768
    Abstract: A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: April 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-lyul Park, Gil-heyun Choi, Suk-chul Bang, Kwang-jin Moon, Dong-chan Lim, Deok-young Jung
  • Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same
    Publication number: 20150108605
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 23, 2015
    Inventors: Jae-Hwa Park, Suk-Chul Bang, Byung-Lyul Park, Kwang-Jin Moon
  • SEMICONDUCTOR DEVICE INCLUDING DECOUPLING CAPACITOR AND METHOD OF FORMING THE SAME
    Publication number: 20150102395
    Abstract: An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Inventors: Jae-Hwa Park, Kwang-Jin Moon, Byung-Lyul Park
  • SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME
    Publication number: 20150093896
    Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Inventors: Kyu-Ha Lee, Ho-Jin Lee, Pil-Kyu Kang, Byung Lyul Park, Hyunsoo Chung, Gilheyun Choi
  • WAFER LOADERS HAVING BUFFER ZONES
    Publication number: 20150068948
    Abstract: Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 12, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yi Koan HONG, Byung Lyul PARK, Jumyong PARK, Jisoon PARK, Kyu-Ha LEE, Siyoung CHOI
  • Semiconductor devices and methods of manufacturing the same
    Patent number: 8969196
    Abstract: A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
    Patent number: 8963336
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a through-via electrode extending through the substrate. The through-via electrode has an interconnection metal layer and a barrier metal layer surrounding a side surface of the interconnection metal layer. One end of the through-via electrode protrudes above the second surface. A spacer insulating layer may be provided on an outer sidewall of the through-via electrode. A through-via electrode pad is connected to the through-via electrode and extends on the spacer insulating layer substantially parallel to the second surface. A first silicon oxide layer and a silicon nitride layer are stacked on the second surface. A thickness of the first silicon oxide layer is greater than a thickness of the silicon nitride layer.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-young Jung, Pil-kyu Kang, Byung-lyul Park, Ji-soon Park, Seong-min Son, Jin-ho An, Ji-hwang Kim
  • Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages
    Patent number: 8957526
    Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Chun, Byung-lyul Park, Hyun-soo Chung, Gil-heyun Choi, Son-kwan Hwang
  • Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices
    Patent number: 8952543
    Abstract: A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Byung-Lyul Park, Hyun-Soo Chung, Gil-Heyun Choi
  • INTEGRATED CIRCUIT DEVICE HAVING THROUGH-SILICON-VIA STRUCTURE AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT DEVICE
    Publication number: 20150028494
    Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 29, 2015
    Inventors: Jae-hwa PARK, Kwang-jin MOON, Byung-lyul PARK, Suk-chul BANG
  • INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE AND DECOUPLING CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150028450
    Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 29, 2015
    Inventors: Jae-hwa PARK, Sung-hee KANG, Kwang-jin MOON, Byung-lyul PARK, Suk-chul BANG
  • Semiconductor devices having through-vias and methods for fabricating the same
    Patent number: 8941216
    Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Ha Lee, Ho-Jin Lee, Pil-Kyu Kang, Byung Lyul Park, Hyunsoo Chung, Gilheyun Choi
  • Semiconductor devices having through-vias and methods for fabricating the same
    Patent number: 8927426
    Abstract: Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Lee, Pil-Kyu Kang, Kyu-Ha Lee, Gilheyun Choi, YongSoon Choi, Byung Lyul Park, Hyunsoo Chung
  • METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES
    Publication number: 20140357077
    Abstract: Provided are methods for fabricating semiconductor devices having through electrodes. The method may comprise forming a polishing stop layer having a multi-layered structure on a substrate, forming a via hole partially penetrating the substrate, providing the substrate with a first cleaning solution to first clean the substrate, providing the substrate with a second cleaning solution to second clean the substrate, the second cleaning solution being different from the first cleaning solution, and forming a through electrode in the via hole.
    Type: Application
    Filed: February 25, 2014
    Publication date: December 4, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SOYOUNG LEE, JIN HO AN, Byung Lyul PARK, JISOON PARK
  • Optical input/output device and method of fabricating the same
    Patent number: 8901694
    Abstract: An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Joong-Han Shin, Byung-Lyul Park, Gil-Heyun Choi
  • Integrated circuit device including through-silicon via structure having offset interface
    Patent number: 8884440
    Abstract: An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-kyoung Kim, Gil-heyun Choi, Byung-lyul Park, Kwang-jin Moon, Kun-sang Park, Dong-chan Lim, Do-sun Lee