Abstract: A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

Abstract: An audio output device and an electronic device are provided. The audio output device includes a plurality of speakers, a terminal connected with a sound source providing device, and a cable connecting the plurality of speakers and the terminal. The cable includes a wire, a flexible element arranged surrounding a portion of the wire, and an insulation member forming an outer sheath of the cable. The flexible element includes a first flexible electrode and a second flexible electrode, and a capacitance of the flexible element changes as the flexible element is deformed.

Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.

Abstract: Semiconductor devices having through-electrodes are provided. The semiconductor devices may include a substrate, a through-electrode penetrating vertically through the substrate, a circuit layer on the substrate and metal lines in the circuit layer. The metal lines may include two first metals on opposing edges of a top surface of the through-electrode and second metals above the top surface of the through-electrode. At least some of the second metals may not vertically overlap the two first metals.

Abstract: Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.

Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract: Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

Abstract: A shielding unit for a plating apparatus may include a shielding plate, a controlling plate and a rotary actuator. The shielding plate may have a plurality of holes configured to permit a passage of an electrolyte therethrough. The controlling plate may make contact with the shielding plate. The controlling plate may have a plurality of controlling holes for controlling an opening ratio of the plurality of holes of the shielding plate. The rotary actuator may rotate the controlling plate to control the opening ratio of the plurality of holes shielding plate.

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

Abstract: Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode.

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.

Abstract: Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.