Patents by Inventor Byung Wook Bae
Byung Wook Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120020Abstract: A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.Type: ApplicationFiled: March 24, 2023Publication date: April 11, 2024Applicant: SK hynix Inc.Inventors: Byung Wook BAE, Jung Ryul AHN
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Publication number: 20230125409Abstract: There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.Type: ApplicationFiled: April 11, 2022Publication date: April 27, 2023Applicant: SK hynix Inc.Inventors: Byung Wook BAE, Eun Seok CHOI
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Publication number: 20220359560Abstract: A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.Type: ApplicationFiled: October 28, 2021Publication date: November 10, 2022Applicant: SK hynix Inc.Inventor: Byung Wook BAE
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Patent number: 9530694Abstract: A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the TSV and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film.Type: GrantFiled: June 30, 2015Date of Patent: December 27, 2016Assignee: SK HYNIX INC.Inventor: Byung Wook Bae
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Patent number: 9343364Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.Type: GrantFiled: January 30, 2015Date of Patent: May 17, 2016Assignee: SK HYNIX INC.Inventor: Byung Wook Bae
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Patent number: 9318393Abstract: A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (TSV) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the TSV so as to determine the presence or absence of metal pollution caused by the TSV.Type: GrantFiled: March 4, 2014Date of Patent: April 19, 2016Assignee: SK HYNIX INC.Inventor: Byung Wook Bae
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Patent number: 9281262Abstract: A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.Type: GrantFiled: September 10, 2012Date of Patent: March 8, 2016Assignee: SK HYNIXInventor: Byung Wook Bae
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Publication number: 20150303109Abstract: A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the TSV and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film.Type: ApplicationFiled: June 30, 2015Publication date: October 22, 2015Inventor: Byung Wook BAE
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Publication number: 20150147878Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.Type: ApplicationFiled: January 30, 2015Publication date: May 28, 2015Inventor: Byung Wook BAE
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Publication number: 20150097185Abstract: A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of device characteristics and reliability. The semiconductor device includes: a semiconductor substrate including an active region defined by a device isolation region; a through silicon via (TSV) formed to pass through the semiconductor substrate; and a test unit formed in the vicinity of the TSV so as to determine the presence or absence of metal pollution caused by the TSV.Type: ApplicationFiled: March 4, 2014Publication date: April 9, 2015Applicant: SK HYNIX INC.Inventor: Byung Wook BAE
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Publication number: 20140327147Abstract: A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface of the semiconductor substrate, a through silicon via (TSV) configured to pass through the semiconductor substrate and the insulation film, and an oxide film formed at a sidewall of the TSV and protruded from the back surface of the semiconductor substrate in a manner that the oxide film partially contacts the insulation film.Type: ApplicationFiled: January 20, 2014Publication date: November 6, 2014Applicant: SK HYNIX INC.Inventor: Byung Wook BAE
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Publication number: 20140264833Abstract: A semiconductor package includes through-chip vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate; and a passivation layer formed on the backside of the semiconductor substrate and planarized corresponding to the surface of the protrusions of the through-chip vias, wherein the passivation layer includes a first insulation layer formed on the side of the protrusions of the through-chip vias and the backside of the semiconductor substrate, and a second insulation layer formed over the first insulation layer.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: SK HYNIX INC.Inventors: Ho-Young SON, Byung-Wook BAE, Jong-Hoon KIM
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Publication number: 20140264848Abstract: A semiconductor package includes through-substrate vias each penetrating through a semiconductor substrate and having a protrusion that is protruded from the backside of the semiconductor substrate, and a passivation layer formed on a sidewall of the protrusion and the backside of the semiconductor substrate, wherein a bottom surface of the protrusion and a bottom surface of the passivation layer are substantially coplanar.Type: ApplicationFiled: January 13, 2014Publication date: September 18, 2014Applicant: SK hynix Inc.Inventors: Ho-Young SON, Byung-Wook BAE, Jong-Hoon KIM, Han-Jun BAE
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Publication number: 20140048937Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.Type: ApplicationFiled: December 18, 2012Publication date: February 20, 2014Applicant: SK HYNIX INC.Inventor: Byung Wook BAE
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Publication number: 20140014957Abstract: A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.Type: ApplicationFiled: September 10, 2012Publication date: January 16, 2014Applicant: SK hynix Inc.Inventor: Byung Wook BAE
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Patent number: 8629033Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.Type: GrantFiled: January 10, 2012Date of Patent: January 14, 2014Assignee: Hynix Semiconductor Inc.Inventor: Byung Wook Bae
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Publication number: 20130078782Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.Type: ApplicationFiled: January 10, 2012Publication date: March 28, 2013Applicant: Hynix Semiconductor Inc.Inventor: Byung Wook BAE
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Patent number: 8405483Abstract: A fuse used in a semiconductor memory device. The fuse is formed with a āXā shape where one circuit may be connected simultaneously to a plurality of other circuits. As a result, a fuse region is reduced, and the cutting number is also decreased, thereby lowering the possibility of defects resulting from cutting errors.Type: GrantFiled: December 23, 2008Date of Patent: March 26, 2013Assignee: Hynix Semiconductor Inc.Inventors: Jeong Soo Kim, Byung Wook Bae
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Patent number: 8217710Abstract: The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.Type: GrantFiled: December 30, 2009Date of Patent: July 10, 2012Assignee: Hynix Semiconductor IncInventor: Byung Wook Bae
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Publication number: 20110001211Abstract: Provided is a fuse of a semiconductor device that includes a Y type fuse and an insulation layer configured to expose the Y type fuse such that an exposed portion of the Y type fuse has a substantially āVā shape. According to the present invention, metal crack is prevented from occurring in a Y type fuse under a high temperature and high humidity condition of a reliability test so that the reliability and competitiveness of semiconductor devices can be improved.Type: ApplicationFiled: December 17, 2009Publication date: January 6, 2011Applicant: Hynix Semiconductor Inc.Inventor: Byung Wook BAE