Abstract: A wiring substrate and semiconductor package including a protection layer, an under-bump pad including an upper part disposed on a top surface of the protection layer and a lower part penetrating the protection layer, a dielectric pattern disposed on the protection layer, and a conductive pattern disposed on the dielectric pattern. The lower part of the under-bump pad is exposed on a bottom surface of the protection layer, and the under-bump pad includes a recess region directed into a bottom surface of the under-bump pad from a top surface of the under-bump pad. The dielectric pattern covers a portion of the under-bump pad and fills the recess region. The conductive pattern includes a pad part disposed on a top surface of the dielectric pattern and a via part that vertically penetrates the dielectric pattern and is coupled to the top surface of the under-bump pad.

Abstract: An interposer including a first redistribution structure; a device stack structure on the first redistribution structure, the device stack structure including a first device die and a second device die on the first device die, and each of the first device die and the second device die including one or more integrated stack capacitor structures; a plurality of first connection members on the first redistribution structure; a molding material on the first redistribution structure, the molding material covering the device stack structure and the plurality of first connection members; and a second redistribution structure on the molding material.

Abstract: An interposer is provided. The interposer includes a first redistribution structure; a device die on the first redistribution structure, the device die having a first surface facing the first redistribution structure and a second surface which is opposite to the first surface; a plurality of first connection members on the second surface of the device die; an insulating member disposed on the second surface of the device die and covering first portions of side surfaces of the plurality of first connection members; a plurality of second connection members on the first redistribution structure; a molding material disposed on the first redistribution structure and covering each of the device die, second portions of the side surfaces of the plurality of first connection members, the insulating member, and the plurality of second connection members; and a second redistribution structure on the molding material.

Abstract: An example semiconductor package includes a first redistribution layer, a bridge chip attached to a top surface of the first redistribution layer, a mold layer on the first redistribution layer and enclosing the bridge chip, a second redistribution layer disposed on the mold layer, a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer, and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer includes a pad layer and an interconnection layer disposed on the pad layer. The pad layer includes a first insulating layer and pads in the first insulating layer. Top surfaces of the pads are exposed to an outside of a top surface of the first insulating layer, and bottom surfaces of the pads are exposed to an outside of a bottom surface of the first insulating layer.

Abstract: A semiconductor package may include a first redistribution layer, bridge dies on an upper surface of the first redistribution layer, a second redistribution layer on the bridge dies and electrically connected to the bridge dies, conductive posts between the first and second redistribution layer, and semiconductor chips on an upper surface of the second redistribution layer. Each bridge die may include connection pads on an upper surface of the bridge dies. A pitch between first connection pads of a first bridge die among the bridge dies may be smaller than a pitch between second connection pads of a second bridge die among the bridge dies. A distance between an upper surface of the first bridge die and a lower surface of the second redistribution layer may be smaller than a distance between an upper surface of the second bridge die and a lower surface of the second redistribution layer.

Abstract: A semiconductor package may include: a first redistribution layer structure; a bridge structure on the first redistribution layer structure; a plurality of conductive pillars on the first redistribution layer structure and side by side with the bridge structure; an encapsulant molding the bridge structure and the plurality of conductive pillars on the first redistribution layer structure; a second redistribution layer structure on the encapsulant, wherein a region of the second redistribution layer structure on the bridge structure is defined as a first region and a region other than the first region is defined as a second region; and a plurality of bonding pads at the first region. A vertical thickness of the first region may be smaller than a vertical thickness of the second region.

Abstract: A semiconductor package may include a lower redistribution layer including a lower wiring and a lower via, an embedded region on the lower redistribution layer, a core layer on the lower redistribution layer and including a core via, and an under bump structure including an under bump pad on a lower surface of the lower redistribution layer and an under bump via connecting the lower wiring and the under bump pad, the under bump pad may overlap the under bump via, the lower via, and the core via in a plan view, and the under bump via may be spaced apart from at least one of the lower via and the core via in the plan view.

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Abstract: The present invention relates to novel heterocyclic compounds useful in preparing drugs for the prevention or treatment of diseases associated with STAT3 protein. Specifically, these drugs are useful in the prevention or treatment of solid tumors, blood cancers, radiation or drug-resistant cancers, metastatic cancers, inflammatory diseases, immune system diseases, diabetes, macular degeneration, papillomavirus infections and tuberculosis.

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Abstract: A semiconductor device includes a plurality of memory chips arranged in a line on a substrate, and a bus connected to the plurality of memory chips and configured to sequentially supply an electrical signal to the plurality of memory chips in accordance with a fly-by topology. An order in which the electrical signal is supplied to the plurality of memory chips is different from an order in which the plurality of memory chips is arranged in the line on the substrate.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.

Abstract: A method of fabricating a semiconductor package includes providing a substrate on a stage, the substrate including semiconductor dies and a modified layer along a partition lane and sequentially having an adhesive film and a base film on a surface thereof so that bottom surfaces of the adhesive film and the base film face the stage and top surfaces of the adhesive film and the base film face away from the stage and the bottom surface of the adhesive film faces the top surface of the base film; separating the semiconductor dies from each other by applying a force to the substrate in a lateral direction; applying a gas pressure to a top surface of each of the semiconductor dies; and irradiating ultraviolet rays toward the adhesive film after applying the gas pressure on the top surface of each of the semiconductor dies.

Abstract: The present invention is directed to a membership-based digital mutual cooperation system and method in which the members of a mutual cooperation group are organized based on a network membership system in which the numbers of provisions of maintenance benefits and recommendation benefits are limited, business profits are generated by mediating products or services that members want to purchase via a joint purchase method, and the generated business profits are distributed to the members of the network membership system in a virtuous-circle fashion. In the membership-based digital mutual cooperation system and method according to the present invention, virtuous-circle relationships are established among all members including a first seller, intermediate sellers, and consumers.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.