Abstract: The disclosed embodiments relate to a system that generates prefetches for a stream of data accesses with multiple strides. During operation, while a processor is generating the stream of data accesses, the system examines a sequence of strides associated with the stream of data accesses. Next, upon detecting a pattern having a single constant stride in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the single constant stride. Similarly, upon detecting a recurring pattern having two or more different strides in the examined sequence of strides, the system issues prefetch instructions to prefetch a sequence of data cache lines consistent with the recurring pattern having two or more different strides.

Abstract: Methods and apparatus for deep microscopic super resolution imaging use two independent and variable focal planes. Movements of fiducial markers imaged using one focal plane are monitored and used to provide real-time or near real-time correction for sample drift. A second focal plane may be used to collect light for super-resolution imaging of a sample. A prototype embodiment has produced low drift when imaging many microns deeper than the fiducial markers.

Abstract: A processor includes an execution pipeline configured to execute instructions for threads, wherein the architectural state of a thread includes a set of register windows for the thread. The processor also includes a physical register file (PRF) containing both speculative and architectural versions of registers for each thread. When an instruction that writes to a destination register enters a rename stage, the rename stage allocates an entry for the destination register in the PRF. When an instruction that has written to a speculative version of a destination register enters a commit stage, the commit stage converts the speculative version into an architectural version. It also deallocates an entry for a previous version of the destination register from the PRF. When a register-window-restore instruction that deallocates a register window enters the commit stage, the commit stage deallocates local and output registers for the deallocated register window from the PRF.

Abstract: A component of an entropy encoding stage of a block processing pipeline (e.g., a CABAC encoder) may, for a block of pixels in a video frame, accumulate counts indicating the number of times each of two possible symbols is used in encoding a syntax element bin. An empirical probability for each symbol, an estimated entropy, and an estimated rate cost for encoding the bin may be computed, dependent on the symbol counts. A pipeline stage that precedes the entropy encoding stage may, upon receiving another block of pixels for the video frame, calculate and use the estimated rate cost when making encoding decisions for the other block of pixels based on a cost function that includes a rate cost term. The symbol counts or empirical probabilities may be passed to the earlier pipeline stage or written to a shared memory, from which components of the earlier stage may obtain them.

Abstract: Systems and methods for improving determination of encoded image data using a video encoding pipeline, which includes a first transcode engine that entropy encodes a first portion of a bin stream to determine a first bit stream including first encoded image data that indicates a first coding group row and that determines first characteristic data corresponding to the first bit stream to facilitate communicating a combined bit stream; and a second transcode engine that entropy encode a second portion of the bin stream to determine a second bit stream including second encoded image data that indicates a second coding group row while the first transcode engine entropy encodes the first portion of the bin stream and that determines second characteristic data corresponding to the second bit stream to facilitate communicating the combined bit stream, which includes the first bit stream and the second bit stream, to a decoding device.

Abstract: Devices and methods for error diffusion and spatiotemporal dithering are provided. By way of example, a method of operating a display includes receiving a pixel input, a set of pixel coordinates, and a current frame number. A kernel and a particular kernel bit of the kernel is selected from a set of kernels, based upon the pixel input, the pixel coordinates, the frame number, or any combination thereof. A dithered output is determined based at least in part upon the kernel bit. When the display is in a diamond pixel configuration, the dithered output is applied in accordance with a diamond pattern formed by red, blue, or red and blue pixel channels.

Abstract: A display control is configured to detect a first condition related to an image frame from source image data. The display control is also configured to compress the image frame iteratively on portions of the image frame to generate a compressed frame. The display control is configured to compress the image frame iteratively when the first condition is detected. Additionally, display control is configured to determine whether to transmit the compressed frame to memory.

Abstract: The disclosed embodiments relate to a method for controlling prefetching in a processor to prevent over-saturation of interfaces in the memory hierarchy of the processor. While the processor is executing, the method determines a bandwidth utilization of an interface from a cache in the processor to a lower level of the memory hierarchy. Next, the method selectively adjusts a prefetch-dropping high-water mark for occupancy of a miss buffer associated with the cache based on the determined bandwidth utilization, wherein the miss buffer stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy, and wherein when the occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

Abstract: Video encoders may determine an initial designation of a mode in which to encode a block of pixels in an early stage of a block processing pipeline. A component of a late stage of the block processing pipeline (one that precedes the transcoder) may determine a different mode designation for the block of pixels based on coded block pattern information, motion vector information, the position of the block in a row of such blocks, the order in which such blocks are processed in the pipeline, or other encoding related syntax elements. The component in the late stage may communicate information to the transcoder usable in coding the block of pixels, such as modified syntax elements or an end of row marker. The transcoder may encode the block of pixels in accordance with the different mode designation or may change the mode again, dependent on the communicated information.

Abstract: A method is provided to remediate defects in first computer program code that can be used to configure a computer to produce code for use by the same or a different computer configured using second computer program code to use the produced code to produce output information, the method comprising: configuring a computer to perform static analysis of the first program to produce an information structure in a non-transitory computer readable storage device that associates a respective code statement of the first program code with a respective context, wherein the context associates a parser state with a potential defect in the produced code; identify a defect in the first computer program code that is associated with the respective code statement; and determining a remediation for the identified defect.

Abstract: The disclosed embodiments provide a system that facilitates prefetching an instruction cache line in a processor. During execution of the processor, the system performs a current instruction cache access which is directed to a current cache line. If the current instruction cache access causes a cache miss or is a first demand fetch for a previously prefetched cache line, the system determines whether the current instruction cache access is discontinuous with a preceding instruction cache access. If so, the system completes the current instruction cache access by performing a cache access to service the cache miss or the first demand fetch, and also prefetching a predicted cache line associated with a discontinuous instruction cache access which is predicted to follow the current instruction cache access.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.

Abstract: A front-support apparatus includes a seat section; and a front support section. The front support section may be substantially perpendicular to the seated section. The front support section may include a top support section, and multiple flanges extending and protruding horizontally from the top support section. The apparatus may be a stand-alone apparatus capable of being placed on a chair via the seat section and held in place on the chair by user weight. Alternatively, the front support section may clamp to a seat of an existing chair to provide support to the user's torso/shoulder area. Alternatively, the apparatus may be integrated with a chair. The apparatus may be adjustable to accommodate users of different sizes.

Abstract: A method of forming fins on a substrate is provided. The method comprises depositing first fin spacers comprising first fin spacer material and second fin spacers comprising second fin spacer material on a plurality of locations on a substrate having a hard mask above the substrate's semiconductor material, wherein the first fin spacers comprise desired first fin spacers and dummy first fin spacers and the second fin spacers comprise desired second fin spacers and dummy second fin spacers. The method further comprises forming fins on the substrate under the first fin spacers and the second fin spacers. The fins comprise a plurality of dummy fins and a plurality of desired fins. The dummy fins comprise a plurality of dummy first fins formed under the dummy first fin spacers and a plurality of dummy second fins formed under the dummy second fin spacers.

Abstract: Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes an array with multiple entries, each of which may be allocated for use by any thread. Control logic detects a load miss to memory, wherein the miss is associated with a latency greater than a given threshold. The load instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the load instruction are held at a given pipeline stage until the load instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the load instruction is being serviced.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a transcode pipeline that provides entropy encoding of binarized syntax elements. More specifically, multiple bins may be encoded in parallel, resulting in increased encoding throughput.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. The video encoding pipeline includes a mode decision block, which selects a first inter-frame prediction mode used to prediction encode a first prediction unit, and a motion estimation block, which receives the first inter-frame prediction mode as feedback from the mode decision block when processing a second prediction unit; determines an initial candidate inter-frame prediction mode of the second prediction unit based at least in part on the first inter-frame prediction mode; and determines a final candidate inter-frame prediction mode of the second prediction unit by performing a first motion estimation search based at least in part on the initial candidate inter-frame prediction mode.

Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data.