Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.

Abstract: A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state.

Abstract: A method of calibrating a plurality of superheat controllers includes attaching a plurality of superheat controllers to a manifold assembly, enclosing the manifold assembly within an environmental chamber, and simultaneously calibrating a pressure sensor within each of the plurality of superheat controllers.

Abstract: An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.

Abstract: Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL)to construct a diode.

Abstract: A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.

Abstract: A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon lines, active and metal lines, or polysilicon and metal lines. The cell size can be very small. At least one of the anti-fuse cells have a thin oxide fabricated before, after, or between a diode in at least one contact holes at the cross points of the interconnect lines. The thin oxide of the anti-fuse cells at the cross points can be selected for rupture by applying supply voltages in the two perpendicular lines. In some embodiments, a diode can be created after thin oxide is ruptured so that explicitly fabricating a diode or opening a contact hole at the cross-point may not be necessary.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.

Abstract: An OTP (One-Time Programmable) element can be fabricated in CMOS FinFET processes are disclosed. The OTP cell can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector is disclosed here. In one embodiment, the OTP element includes a MOS gate with at least one portion of the MOS gate can have at least one extended area to accelerate programming. An extended area is an extension of the OTP element beyond two nearest cathode and anode contacts and are longer than required by design rules. The extended area can also have reduced or substantially no current flowing through. The selector can be built with a MOS gate to divide at least one fin structure into two different active regions. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.

Abstract: An integrated One-Time Programmable (OTP) memory to emulate an Multiple-Time Programmable (MTP) memory with a built-in program count tracking and block address mapping is disclosed. The integrated OTP memory has at least one non-volatile block register and count register to respectively store block sizes and program counts for different block/count configurations. The count register can be programmed before each round of programming occurs to indicate a new block for access. The integrated OTP memory also can generate a block address based on values from the count and block registers. By combining the block address with the lower bits of an input address, a final address can be generated and used to access different blocks (associated with different program counts) in the OTP memory to mimic an MTP memory.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices. An OTP device can have at least one OTP element coupled to at least one diode in a memory cell. With a metal fuse is used by the OTP element, at least one contact and/or a plurality of vias can be built (possibly with use of one or more jumpers) in the program path to generate more Joule heat to assist with programming. The jumpers are conductive and can be formed of metal, metal gate, local interconnect, polymetal, etc. The metal fuse can also have an extended area that is longer than required by design rules for enhanced programmability. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof.

Abstract: A system and method is illustrated for providing secure credential using a secure credential package stored on a client device and at least one key stored in a corporate network. In embodiments, an access connector receives credentials and a device unique identifier from the client device over a secure link, obtain the at least one key from the corporate network, apply the at least one key to the credentials and the device unique identifier to generate the secure credential package including the encrypted credential and the device unique identifier, send the secure credential package to the client device over the secure link, upon receiving the secure credential package from the client device, retrieve the at least one key via the key manager, decrypting the secure credential package using the at least one key to obtain the credentials, and validate the credentials against a user directory located in the corporate network.

Abstract: A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.

Abstract: Systems and methods for collecting, selecting, and displaying an image or image set in a network based environment are described. The systems and methods can collect multiple images for any given item from multiple sources, select a desired image (or set of images) that best depicts that item, and then display that selected image (or image set) in the network based environment. The desired image (or image set) that best depicts the item can be selected using any number or combination of pre-selected criteria. By using the pre-selected criteria, the process needs no manual intervention, and can therefore be automated or semi-automated to save both time and cost.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

Abstract: A Power-On-Reset circuit is disclosed to generate a POR signal when a supply voltage (e.g., VDD) is ramping up and has exceeded a threshold voltage. The POR circuit can include a startup circuit, a reference generator, a comparator, and a latch. The startup circuit can be initialized into an on state and can serve to turn on all other circuit blocks of the POR circuit. The reference generator can then generate at least one temperature-compensated reference voltage. The comparator can compare the reference voltage with the supply voltage or a supply voltage following signal to output a Power-On-Signal (POS). After the POS has been asserted and latched, the startup circuit can be reset and the other circuit blocks of the POR circuit can be powered down.

Abstract: At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state.

Abstract: A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines.

Abstract: Circuits and systems for concurrently programming a plurality of OTP cells in an OTP memory are disclosed. Each OTP cell can have an electrical fuse element coupled a program selector having a control terminal. The control terminals of a plurality of OTP cells can be coupled to a plurality of local wordlines, and a plurality of the local wordlines can be coupled to at least one global wordline. A plurality of banks of bitlines can have each bitline coupled to a plurality of the OTP cells via the control terminal of the program selector. A plurality of bank selects can enable turning on the wordlines or bitlines in a bank. A plurality of the OTP cells can be configured to be programmable concurrently into a different logic state by applying voltages to at least one selected global wordline and at least one selected bitline to a plurality of the selected OTP cells in a plurality of banks, if a plurality of banks are enabled.