Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: A vehicle includes a plurality of brake assemblies and a plurality of electronic brake system (EBS) controllers. The brake assemblies each include an electro-mechanical actuator configured to adjust a torque force applied to a wheel of the vehicle. The EBS controllers are located remotely from one another. Each EBS controller has integrated therein an electronic actuator driver unit that includes an electronic power circuit configured to drive at least one of the electro-mechanical actuators. A first EBS controller is configured to drive a first group of electro-mechanical actuators, and a second EBS controller is configured to drive a second group of electro-mechanical actuators that exclude the electro-mechanical actuators of the first group.

Abstract: A brake pedal emulator for a brake-by-wire system of a vehicle extends and connects between a support structure and a brake pedal operatively engaged to the support structure. The brake pedal emulator includes a hydraulic cylinder having a magneto-rheological hydraulic fluid and an electrical element configured to carry an electrical current for controlling a viscosity of the magneto-rheological hydraulic fluid and thereby controlling a first force exerted by the hydraulic cylinder when actuated by the brake pedal.

Abstract: A personal watercraft auto-return system includes a user device having a rider location determination unit, a user interface, and a communication unit. The system also includes an autopilot unit that is positioned within a personal watercraft. The autopilot unit including a steering unit for controlling the steering the watercraft, and a controller having a processor and memory for controlling the engine and throttle controls of the watercraft. The controller selectively activates the steering unit, engine, and throttle of the personal watercraft to navigate to the location of the user device upon receiving a request from the user interface.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: A vehicle includes a plurality of electronic brake system (EBS) controllers configured to detect at least one braking event, and a plurality of brake assemblies. Each brake assembly is coupled to a respective wheel of the vehicle and includes an enhanced smart actuator. The enhanced smart actuator further includes an electro-mechanical actuator, and at least one power circuit. The electro-mechanical actuator is configured to adjust a torque force applied to the respective wheel. The at least one electronic power circuit is configured to output a high-frequency switched high-power current drive signal that drives the electro-mechanical actuator. The EBS controllers control a first group of enhanced smart actuators independently from a second group of enhanced smart actuators that exclude the enhanced smart actuators of the first group.

Abstract: A vehicle with a fault tolerant electronic brake-by-wire (BBW) system includes a plurality of brake assemblies that control braking of a respective wheel of the vehicle. The brake assemblies include a first brake assembly and a second brake assembly. The first brake assembly is integrated with at least one enhanced brake actuator assembly including a first electronic actuator driver circuit in signal communication with a first electro-mechanical actuator. The first brake assembly is configured to adjust a brake force applied to a first wheel of the vehicle. The second brake assembly is integrated with at least one enhanced smart brake actuator assembly including a first actuator controller in signal communication with a second electronic actuator driver circuit. The second electronic actuator driver circuit is in signal communication with a second electro-mechanical actuator that is configured to adjust a brake force applied to a second wheel of the vehicle.

Abstract: A vehicle includes a plurality of brake assemblies, and a brake request input device. Each brake assembly is coupled to a respective wheel of the vehicle and is configured to control braking of the respective wheel. The brake request input device is configured to output an electronic brake request signal indicating a request to brake at least one of the wheels. Each brake assembly has integrated therein an enhanced smart actuator unit that includes an electronic actuator controller configured to control a braking torque applied to the respective wheel in response to receiving the brake request signal.

Abstract: A vehicle includes a plurality of brake assemblies and a plurality of electronic brake system (EBS) controllers. The brake assemblies each include an electro-mechanical actuator configured to adjust a torque force applied to a wheel of the vehicle. The EBS controllers are located remotely from one another. Each EBS controller has integrated therein an electronic actuator driver unit that includes an electronic power circuit configured to drive at least one of the electro-mechanical actuators. A first EBS controller is configured to drive a first group of electro-mechanical actuators, and a second EBS controller is configured to drive a second group of electro-mechanical actuators that exclude the electro-mechanical actuators of the first group.

Abstract: A vehicle includes a plurality of brake assemblies configured to control braking of a respective wheel of the vehicle. The brake assemblies includes a first brake assembly integrated with a smart actuator unit including a first actuator controller and a first electro-mechanical actuator that is configured to adjust a brake force applied to a first wheel coupled to the first brake assembly. A second brake assembly excludes an actuator controller and has installed therein a second electro-mechanical actuator that is configured to adjust a brake force applied to a second wheel coupled to the second brake assembly. At least one electronic actuator driver unit is remotely located from the first and second brake assemblies, and is configured to output a high-power signal that drives the first and second electro-mechanical actuators in response to receiving a digital command signal from the first actuator controller.

Abstract: A vehicle includes a plurality of brake assemblies and a plurality of electrical power circuits. Each brake assembly includes an electro-mechanical actuator configured to adjust a torque force applied to a wheel of the vehicle. The electrical power circuits are located remotely from one another. Each power circuit is configured to drive a respective actuator. The vehicle further includes a first electronic brake system (EBS) controller and a second EBS controller. The first EBS controller is configured to output a first data command signal to control a first group of power circuits among the plurality of power circuits. The second EBS controller is configured to output a second data command signal to control a second group of power circuits among the plurality of power circuits. The second group excludes the power circuits from the first group.

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.

Abstract: A sacrificial anode assembly for cathodically protecting and/or passivating a metal section, comprising: (a) a cell, which has an anode and a cathode arranged so as to not be in electronic contact with each other but so as to be in ionic contact with each other such that current can flow between the anode and the cathode; (b) a connector attached to the anode of the cell for electrically connecting the anode to the metal section to be cathodically protected; and (c) a sacrificial anode electrically connected in series with the cathode of the cell; wherein the cell is otherwise isolated from the environment such that current can only flow into and out of the cell via the sacrificial anode and the connector. The invention also provides a method of cathodically protecting metal in which such a sacrificial anode assembly is cathodically attached to the metal via the connector of the assembly, and a reinforced concrete structure wherein some or all of the reinforcement is cathodically protected by such a method.