Abstract: Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Abstract: A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

Abstract: The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.

Abstract: Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.

Abstract: A cable management assembly for managing cables of rack-mounted computers may include: a base member selectively attachable to a structural member of a computer rack; and a sliding member comprising a cable retention area, wherein the sliding member is configured for connection to the base member by one or more mating connection components, wherein the one or more mating connection components allow for a limited degree of movement of the sliding member relative to the base member.

Abstract: A hinge mechanism for attaching ear accessories to a helmet allows an accessory to be attached at a point outside the helmet shell utilizing, for example, a slidable mounting rail, and to reach under the edge of the helmet shell so that the accessory is supported in contact with the wearer's head. The hinge mechanism is well suited for use in connection with military helmets that have a “bulge” or protrusion over the ear.

Abstract: A mixed-signal integrated circuit (IC), including: a voltage booster that includes one or more charge pump devices configured to receive an input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.

Abstract: The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.

Abstract: Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Abstract: An inventive system related to implementation of dynamic virtual local area network (VLAN) assignment and provisioning in communication networks. The inventive system enables per-room 802.1q VLANs that are enforced through 802.1X distribution equipment. This inventive system enables facilities such as hotels to implement per-room VLANs to increase security and efficiency in handling a plurality of devices brought in by guests as well as devices that are provided by the facility itself.

Abstract: Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Abstract: A cable management assembly for managing cables of rack-mounted computers may include: a base member selectively attachable to a structural member of a computer rack; and a sliding member comprising a cable retention area, wherein the sliding member is configured for connection to the base member by one or more mating connection components, wherein the one or more mating connection components allow for a limited degree of movement of the sliding member relative to the base member.

Abstract: A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.

Abstract: The present invention is a method and apparatus for narrative content generation using narrative frameworks by receiving a first phrase variation and a second phrase variation and displaying an error indication when the first phrase variation fails to satisfy a criterion relative to the second phrase variation. If there is an error indication, alternate phrase variations are received and compared against the first phrase variation until an alternate phrase variation is selected that has no error indication. Additionally, multiple sets of operators for updating one or more narrative phrases selected for inclusion in the narrative content framework may be utilized to update selected phrases after inclusion in the narrative framework but prior to finalizing the narrative content to be output.

Abstract: Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.

Abstract: Disclosed is a plunger for use in a sucker-rod pumping system. The plunger reciprocates within a barrel. The plunger comprises first, second, and third sections, in which the first and third sections are sealed against the barrel and in which a second section is between the first and third sections and in some embodiments may be a pull tube. A through passage for production fluid is provided, along with a pressure balancing chamber that is connected to the through passage via a sand snare, where the pressure balancing chamber is operable to equalize pressure on longitudinal sides of the seals, whereas the sand snare operates to restrain solids from reaching the pressure balancing chamber from the through passage (which is carrying the production fluid) and thereby create a slippage flow in the pressure balancing chamber, which equalizes pressure between the balancing chamber and the plunger's through passage.