Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A method for helium mass spectrometric fine-leak test is based on quantitative determination of maximum test-waiting time, which gives a method for quantitative determination of the maximum test-waiting time for fine-leak test during a helium mass spectrometric test process of the sealability, and gives a method for determining the criterion for measured leak rate by taking the minimum helium gas exchange time constant, i.e., a rigour grade ?Hemin, of an acceptable sealed electronic component as a basic criterion for helium mass spectrometric fine-leak test. Based on the inventive method for quantitative determination of the maximum test-waiting time, for most of the cavity volume ranges, the maximum test-waiting time that is determined accurately may be much longer than 1 hour or 0.5 hour as determined qualitatively by the existing related standards.

Abstract: An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: One signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is arranged to perform a notch filtering operation upon the signal output for generating a filtered signal output. Another signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is enabled for performing a notch filtering operation upon the signal output when the signal processing apparatus operates in a first operational mode, and the notch filtering block is disabled when the signal processing apparatus operates in a second operational mode.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.

Abstract: One signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is arranged to perform a notch filtering operation upon the signal output for generating a filtered signal output. Another signal processing apparatus includes a sigma-delta modulating block and a notch filtering block. The sigma-delta modulating block is arranged to perform a sigma-delta modulation upon a signal input and accordingly generate a signal output. The notch filtering block is enabled for performing a notch filtering operation upon the signal output when the signal processing apparatus operates in a first operational mode, and the notch filtering block is disabled when the signal processing apparatus operates in a second operational mode.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: An RF transmitter (104) includes a shared local oscillator circuit (126), transmit path circuitry (120, 122, 124), a divider (134), and a lowpass filter (322). The shared local oscillator circuit (126) generates a shared LO signal (116). The transmit path circuitry (120, 122, 124) mixes a baseband signal (107) and an IF mixing signal (116) to provide an IF signal (112), and converts the IF signal (112) to an RF transmit signal (105) at a desired frequency using an RF mixing signal received at a mixing input thereof. The divider (134) divides the shared LO signal (116) to provide an unfiltered RF mixing signal. The lowpass filter (322) has an input for receiving the unfiltered RF mixing signal, and an output coupled to the mixing input of the transmit path circuitry (120, 122, 124) for providing the RF mixing signal.

Abstract: An apparatus comprises a circuit having a power supply node and a linear regulator configured to provide a regulated voltage at the power supply node of the circuit. The apparatus further comprises a switching regulator configured to provide input power to the linear regulator from a power source such as a battery. In some implementations, the circuit is a transceiver circuit.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract: A transceiver system including a common receiver and transmitter oscillator. The transceiver system may include transmitter circuitry, receiver circuitry, and a first oscillator. The first oscillator may provide a transmit frequency to a mixer in the transmitter circuitry to generate a transmitter RF signal. Furthermore, the first oscillator may also provide the transmit frequency to a first stage mixer in the receiver circuitry to down-convert a receiver RF signal from a receive frequency to an intermediate frequency (IF). The receiver circuitry may include a second oscillator and a second stage mixer. The second oscillator may provide an IF frequency to the second stage mixer to down-convert receiver signals at IF to a lower frequency. The receiver circuitry may filter out transmitter RF feedthrough signals without using a SAW filter. The transmitter circuitry, the receiver circuitry, and the first oscillator may be included in a single IC.