Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.

Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.