Patents by Inventor CARL H. NAYLOR

CARL H. NAYLOR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230069567
    Abstract: Techniques are provided herein for forming interconnect structures, such as conductive vias or contacts, that are protected from subsequent processing that includes reactive gas or plasma. A conductive via or contact within an interconnect layer may be formed with a capping layer having a different material to protect the underlying metal material from reacting with certain reactive gas or plasma elements. In some examples, a ruthenium capping layer is formed over a copper via to protect the copper. Other capping layer materials may include tungsten, cobalt, or molybdenum. In some embodiments, the entire conductive via may be formed using one of ruthenium, tungsten, cobalt, or molybdenum, to avoid the use of more reactive metals, such as copper. The capping layer (or less reactive metals) are used to protect the via during a barrier layer doping process that uses a gas or plasma including a chalcogen element (e.g., sulfur and/or selenium).
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventor: Carl H. Naylor
  • Patent number: 11062995
    Abstract: An integrated circuit includes a base with one or more semiconductor devices. An insulating material is over the base and an interconnect structure is over the base. The interconnect structure includes vertical conductors extending through the insulating material in a spaced-apart arrangement. The interconnect structure comprises a conductor and a chalcogen, the chalcogen present in an amount of up to 5 atomic percent. In some embodiments, the chalcogen is present in an amount less than 2 atomic percent or less than 1 atomic percent.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Carl H. Naylor, Mauro J. Kobrinsky
  • Publication number: 20210111129
    Abstract: An integrated circuit includes a base with one or more semiconductor devices. An insulating material is over the base and an interconnect structure is over the base. The interconnect structure includes vertical conductors extending through the insulating material in a spaced-apart arrangement. The interconnect structure comprises a conductor and a chalcogen, the chalcogen present in an amount of up to 5 atomic percent. In some embodiments, the chalcogen is present in an amount less than 2 atomic percent or less than 1 atomic percent.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 15, 2021
    Applicant: INTEL CORPORATION
    Inventors: Carl H. Naylor, Mauro J. Kobrinsky
  • Publication number: 20200395406
    Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: EMILY WALKER, CARL H. NAYLOR, KAAN OGUZ, KEVIN L. LIN, TANAY GOSAVI, CHRISTOPHER J. JEZEWSKI, CHIA-CHING LIN, BENJAMIN W. BUFORD, DMITRI E. NIKONOV, JOHN J. PLOMBON, IAN A. YOUNG, NORIYUKI SATO