Patents by Inventor Carl J. Radens
Carl J. Radens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220406658Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.Type: ApplicationFiled: June 6, 2022Publication date: December 22, 2022Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
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Patent number: 11380583Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.Type: GrantFiled: February 22, 2021Date of Patent: July 5, 2022Assignee: TESSERA LLCInventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
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Patent number: 11372701Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.Type: GrantFiled: August 19, 2019Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
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Patent number: 11348832Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.Type: GrantFiled: July 2, 2019Date of Patent: May 31, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
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Publication number: 20210202313Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.Type: ApplicationFiled: February 22, 2021Publication date: July 1, 2021Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
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Patent number: 10930553Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.Type: GrantFiled: January 25, 2019Date of Patent: February 23, 2021Assignee: Tessera, Inc.Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
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Patent number: 10727122Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.Type: GrantFiled: December 8, 2014Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
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Patent number: 10707224Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.Type: GrantFiled: May 24, 2018Date of Patent: July 7, 2020Assignee: International Business Machines CorporatinoInventors: Ramachandra Divakaruni, Arvind Kumar, Carl J. Radens
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Patent number: 10700214Abstract: Processes and overturned thin film device structures generally include a gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the gate and the source/drain contacts include a self-aligned step height.Type: GrantFiled: April 5, 2018Date of Patent: June 30, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10546936Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate.Type: GrantFiled: February 26, 2019Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Carl J Radens, Richard Q Williams
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Publication number: 20190370100Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
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Publication number: 20190326170Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: Benjamin C. BACKES, Brian A. COHEN, Joyeeta NAG, Carl J. RADENS
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Patent number: 10395984Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.Type: GrantFiled: March 15, 2016Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
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Patent number: 10388639Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: November 3, 2017Date of Patent: August 20, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10387235Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.Type: GrantFiled: May 23, 2016Date of Patent: August 20, 2019Assignee: International Buisness Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
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Patent number: 10374046Abstract: A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.Type: GrantFiled: January 2, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Carl J Radens, Richard Q Williams
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Patent number: 10347617Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: September 5, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Publication number: 20190189760Abstract: A structure of a semiconductor device is described. A semiconductor device includes a transistor which further includes a gate structure, a source region and a drain region disposed on a first surface of a substrate. A wiring layer of conductive material is disposed over a second surface of the substrate. The second surface of the substrate is located opposite to the first surface of the substrate. A set of contact studs including a first contact stud which extends completely through the source region and through the substrate to a first respective portion of the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the drain region and through the substrate to a second respective portion of the wiring layer. A gate contact stud electrically couples the gate structure and extends completely through the substrate to a third respective portion of the wiring layer disposed over the second surface of the substrate.Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Inventors: Carl J Radens, Richard Q Williams
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Patent number: 10319870Abstract: An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.Type: GrantFiled: September 21, 2010Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Timothy J. Dalton, Maxime Darnon, Rainer Krause, Gerd Pfeiffer, Kevin Prettyman, Carl J. Radens, Brian C. Sapp
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Publication number: 20190172748Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.Type: ApplicationFiled: January 25, 2019Publication date: June 6, 2019Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang